From: Bjorn Helgaas <helgaas@kernel.org>
To: root <root@hu-msarkar-hyd.qualcomm.com>
Cc: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org,
conor+dt@kernel.org, quic_nitegupt@quicinc.com,
quic_shazhuss@quicinc.com, quic_ramkri@quicinc.com,
quic_nayiluri@quicinc.com, quic_krichai@quicinc.com,
quic_vbadigan@quicinc.com, "Nitesh Gupta" <nitegupt@quicinc.com>,
"Mrinmay Sarkar" <quic_msarkar@quicinc.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 3/3] PCI: qcom: Add support for detecting controller level PCIe errors
Date: Thu, 22 Feb 2024 06:38:16 -0600 [thread overview]
Message-ID: <20240222123816.GA1633656@bhelgaas> (raw)
In-Reply-To: <20240221185017.GA1536431@bhelgaas>
On Wed, Feb 21, 2024 at 12:50:17PM -0600, Bjorn Helgaas wrote:
> On Wed, Feb 21, 2024 at 07:34:04PM +0530, root wrote:
> > From: Nitesh Gupta <nitegupt@quicinc.com>
> >
> > Synopsys Controllers provide capabilities to detect various controller
> > level errors. These can range from controller interface error to random
> > PCIe configuration errors. This patch intends to add support to detect
> > these errors and report it to userspace entity via sysfs, which can take
> > appropriate actions to mitigate the errors.
> > +static void qcom_pcie_enable_error_reporting_2_7_0(struct qcom_pcie *pcie)
> > +{
> > + ...
>
> > + val = readl(pci->dbi_base + DBI_DEVICE_CONTROL_DEVICE_STATUS);
> > + val |= (PCIE_CAP_CORR_ERR_REPORT_EN | PCIE_CAP_NON_FATAL_ERR_REPORT_EN |
> > + PCIE_CAP_FATAL_ERR_REPORT_EN | PCIE_CAP_UNSUPPORT_REQ_REP_EN);
> > + writel(val, pci->dbi_base + DBI_DEVICE_CONTROL_DEVICE_STATUS);
>
> Is there any way to split the AER part (specified by the PCIe spec)
> from the qcom-specific (or dwc-specific) part? This looks an awful
> lot like pci_enable_pcie_error_reporting(), and we should do this in
> the PCI core in a generic way if possible.
>
> > + val = readl(pci->dbi_base + DBI_ROOT_CONTROL_ROOT_CAPABILITIES_REG);
> > + val |= (PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN | PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN |
> > + PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN);
> > + writel(val, pci->dbi_base + DBI_ROOT_CONTROL_ROOT_CAPABILITIES_REG);
More to the point: why do we need to do this in the qcom driver at
all? Why is pci_enable_pcie_error_reporting() not enough?
Bjorn
next prev parent reply other threads:[~2024-02-22 12:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 14:04 [PATCH v1 0/3] Add support for detecting Controller Level PCIe Errors root
2024-02-21 14:04 ` [PATCH v1 1/3] dt-bindings: PCI: qcom: Add global irq support for SA8775p root
2024-02-21 14:28 ` Krzysztof Kozlowski
2024-02-21 14:31 ` Konrad Dybcio
2024-02-21 14:33 ` Krzysztof Kozlowski
2024-02-22 13:46 ` Mrinmay Sarkar
2024-02-22 14:19 ` Krzysztof Kozlowski
2024-02-21 14:04 ` [PATCH v1 2/3] arm64: dts: qcom: sa8775p: Enable " root
2024-02-21 14:04 ` [PATCH v1 3/3] PCI: qcom: Add support for detecting controller level PCIe errors root
2024-02-21 14:35 ` Krzysztof Kozlowski
2024-02-21 18:50 ` Bjorn Helgaas
2024-02-22 12:38 ` Bjorn Helgaas [this message]
2024-02-21 21:00 ` Frank Li
2024-02-22 11:01 ` kernel test robot
2024-02-22 12:39 ` kernel test robot
2024-02-22 5:22 ` [PATCH v1 0/3] Add support for detecting Controller Level PCIe Errors Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240222123816.GA1633656@bhelgaas \
--to=helgaas@kernel.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=nitegupt@quicinc.com \
--cc=quic_krichai@quicinc.com \
--cc=quic_msarkar@quicinc.com \
--cc=quic_nayiluri@quicinc.com \
--cc=quic_nitegupt@quicinc.com \
--cc=quic_ramkri@quicinc.com \
--cc=quic_shazhuss@quicinc.com \
--cc=quic_vbadigan@quicinc.com \
--cc=robh@kernel.org \
--cc=root@hu-msarkar-hyd.qualcomm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox