[PATCH v1 14/20] perf jevents: Add Miss Level Parallelism (MLP) metric for Intel

Ian Rogers
2024-02-29T00:18:57Z

Number of oustanding load misses per cycle.

Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/intel_metrics.py | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py
index fef40969a4b8..e373f87d499d 100755
--- a/tools/perf/pmu-events/intel_metrics.py
+++ b/tools/perf/pmu-events/intel_metrics.py
@@ -617,6 +617,20 @@ def IntelL2() -> Optional[MetricGroup]:
], description = "L2 data cache analysis")

+def IntelMlp() -> Optional[Metric]:
+ try:
+ l1d = Event("L1D_PEND_MISS.PENDING")
+ l1dc = Event("L1D_PEND_MISS.PENDING_CYCLES")
+ except:
+ return None
+
+ l1dc = Select(l1dc / 2, Literal("#smt_on"), l1dc)
+ ml = d_ratio(l1d, l1dc)
+ return Metric("mlp",
+ "Miss level parallelism - number of oustanding load misses per cycle (higher is better)",
+ ml, "load_miss_pending/cycle")
+
+
def IntelPorts() -> Optional[MetricGroup]:
pipeline_events = json.load(open(f"{os.path.dirname(os.path.realpath(__file__))}"
f"/arch/x86/{args.model}/pipeline.json"))
@@ -798,6 +812,7 @@ all_metrics = MetricGroup("", [
IntelIlp(),
IntelL2(),
IntelLdSt(),
+ IntelMlp(),
IntelPorts(),
IntelSwpf(),
])
--
2.44.0.278.ge034bb2e1d-goog