Re: [PATCH v6 2/3] PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP

Manivannan Sadhasivam
2024-03-10T12:57:09Z

On Wed, Mar 06, 2024 at 06:41:11PM +0530, Mrinmay Sarkar wrote:
> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
> the requester is indicating that no cache coherency issues exist for
> the addressed memory on the host i.e., memory is not cached. But in
> reality, requester cannot assume this unless there is a complete
> control/visibility over the addressed memory on the host.
>
> And worst case, if the memory is cached on the host, it may lead to
> memory corruption issues. It should be noted that the caching of memory
> on the host is not solely dependent on the NO_SNOOP attribute in TLP.
>
> So to avoid the corruption, this patch overrides the NO_SNOOP attribute
> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
> needed for other upstream supported platforms since they do not set
> NO_SNOOP attribute by default.
>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>

Same nit as previous patch. With that addressed,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

> ---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 89d06a3..aa8e979 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -47,6 +47,7 @@
> #define PARF_DBI_BASE_ADDR_HI 0x354
> #define PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
> +#define PARF_NO_SNOOP_OVERIDE 0x3d4
> #define PARF_ATU_BASE_ADDR 0x634
> #define PARF_ATU_BASE_ADDR_HI 0x638
> #define PARF_SRIS_MODE 0x644
> @@ -86,6 +87,10 @@
> #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
> #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
>
> +/* PARF_NO_SNOOP_OVERIDE register fields */
> +#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
> +#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
> +
> /* PARF_DEVICE_TYPE register fields */
> #define PARF_DEVICE_TYPE_EP 0x0
>
> @@ -152,9 +157,11 @@ enum qcom_pcie_ep_link_status {
> /**
> * struct qcom_pcie_ep_cfg - Per SoC config struct
> * @hdma_support: HDMA support on this SoC
> + * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping
> */
> struct qcom_pcie_ep_cfg {
> bool hdma_support;
> + bool override_no_snoop;
> };
>
> /**
> @@ -175,6 +182,7 @@ struct qcom_pcie_ep_cfg {
> * @num_clks: PCIe clocks count
> * @perst_en: Flag for PERST enable
> * @perst_sep_en: Flag for PERST separation enable
> + * @cfg: PCIe EP config struct
> * @link_status: PCIe Link status
> * @global_irq: Qualcomm PCIe specific Global IRQ
> * @perst_irq: PERST# IRQ
> @@ -202,6 +210,7 @@ struct qcom_pcie_ep {
> u32 perst_en;
> u32 perst_sep_en;
>
> + const struct qcom_pcie_ep_cfg *cfg;
> enum qcom_pcie_ep_link_status link_status;
> int global_irq;
> int perst_irq;
> @@ -497,6 +506,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
> val |= BIT(8);
> writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
>
> + /* Override NO_SNOOP attribute in TLP to enable cache snooping */

Same comment as previous patch.

- Mani

> + if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)
> + writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
> + pcie_ep->parf + PARF_NO_SNOOP_OVERIDE);
> +
> return 0;
>
> err_disable_resources:
> @@ -811,7 +825,6 @@ static const struct dw_pcie_ep_ops pci_ep_ops = {
>
> static int qcom_pcie_ep_probe(struct platform_device *pdev)
> {
> - const struct qcom_pcie_ep_cfg *cfg;
> struct device *dev = &pdev->dev;
> struct qcom_pcie_ep *pcie_ep;
> char *name;
> @@ -826,8 +839,8 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
> pcie_ep->pci.ep.ops = &pci_ep_ops;
> pcie_ep->pci.edma.nr_irqs = 1;
>
> - cfg = of_device_get_match_data(dev);
> - if (cfg && cfg->hdma_support) {
> + pcie_ep->cfg = of_device_get_match_data(dev);
> + if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) {
> pcie_ep->pci.edma.ll_wr_cnt = 8;
> pcie_ep->pci.edma.ll_rd_cnt = 8;
> pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE;
> @@ -893,6 +906,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev)
>
> static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
> .hdma_support = true,
> + .override_no_snoop = true,
> };
>
> static const struct of_device_id qcom_pcie_ep_match[] = {
> --
> 2.7.4
>

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