From: Li Ming <ming4.li@intel.com>
To: dan.j.williams@intel.com, rrichter@amd.com, terry.bowman@amd.com
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Li Ming <ming4.li@intel.com>
Subject: [RFC PATCH 5/6] cxl: Use __free() for cxl_pci/mem_find_port() to drop put_device()
Date: Wed, 13 Mar 2024 08:36:01 +0000 [thread overview]
Message-ID: <20240313083602.239201-6-ming4.li@intel.com> (raw)
In-Reply-To: <20240313083602.239201-1-ming4.li@intel.com>
Introduce a new helper function called put_cxl_port() to instead of the
put_device() in order to release the device reference of struct cxl_port
got via get_device() in cxl_pci/mem_find_port().
Besides, use scope-based resource management __free() to drop the open
coded put_device() for each cxl_pci/mem_find_port().
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Li Ming <ming4.li@intel.com>
---
drivers/cxl/core/pci.c | 6 ++----
drivers/cxl/core/port.c | 9 +++++++++
drivers/cxl/cxl.h | 2 ++
drivers/cxl/mem.c | 5 ++---
drivers/cxl/pci.c | 12 +++++-------
5 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 6c9c8d92f8f7..7254484330d2 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -902,15 +902,13 @@ static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
struct pci_dev *pdev = to_pci_dev(cxlds->dev);
struct aer_capability_regs aer_regs;
struct cxl_dport *dport;
- struct cxl_port *port;
int severity;
+ struct cxl_port *port __free(put_cxl_port) =
+ cxl_pci_find_port(pdev, &dport);
- port = cxl_pci_find_port(pdev, &dport);
if (!port)
return;
- put_device(&port->dev);
-
if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
return;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index e59d9d37aa65..6e2fc2fce7c9 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1671,6 +1671,15 @@ struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);
+void put_cxl_port(struct cxl_port *port)
+{
+ if (!port)
+ return;
+
+ put_device(&port->dev);
+}
+EXPORT_SYMBOL_NS_GPL(put_cxl_port, CXL);
+
static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
struct cxl_port *port, int *target_map)
{
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b6017c0c57b4..476158782e3e 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -743,6 +743,8 @@ struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
struct cxl_dport **dport);
struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
struct cxl_dport **dport);
+void put_cxl_port(struct cxl_port *port);
+DEFINE_FREE(put_cxl_port, struct cxl_port *, if (_T) put_cxl_port(_T))
bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index c5c9d8e0d88d..5aaa8ee2a46d 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -109,7 +109,6 @@ static int cxl_mem_probe(struct device *dev)
struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct device *endpoint_parent;
- struct cxl_port *parent_port;
struct cxl_dport *dport;
struct dentry *dentry;
int rc;
@@ -146,7 +145,8 @@ static int cxl_mem_probe(struct device *dev)
if (rc)
return rc;
- parent_port = cxl_mem_find_port(cxlmd, &dport);
+ struct cxl_port *parent_port __free(put_cxl_port) =
+ cxl_mem_find_port(cxlmd, &dport);
if (!parent_port) {
dev_err(dev, "CXL port topology not found\n");
return -ENXIO;
@@ -170,7 +170,6 @@ static int cxl_mem_probe(struct device *dev)
rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport);
unlock:
device_unlock(endpoint_parent);
- put_device(&parent_port->dev);
if (rc)
return rc;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 4fd1f207c84e..d0ec8c5b1e99 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -473,23 +473,21 @@ static bool is_cxl_restricted(struct pci_dev *pdev)
static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
struct cxl_register_map *map)
{
- struct cxl_port *port;
struct cxl_dport *dport;
resource_size_t component_reg_phys;
+ struct cxl_port *port __free(put_cxl_port) =
+ cxl_pci_find_port(pdev, &dport);
+
+ if (!port)
+ return -EPROBE_DEFER;
*map = (struct cxl_register_map) {
.host = &pdev->dev,
.resource = CXL_RESOURCE_NONE,
};
- port = cxl_pci_find_port(pdev, &dport);
- if (!port)
- return -EPROBE_DEFER;
-
component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);
- put_device(&port->dev);
-
if (component_reg_phys == CXL_RESOURCE_NONE)
return -ENXIO;
--
2.40.1
next prev parent reply other threads:[~2024-03-13 9:04 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-13 8:35 [RFC PATCH 0/6] Add support for root port RAS error handling Li Ming
2024-03-13 8:35 ` [RFC PATCH 1/6] PCI/RCEC: Introduce pcie_walk_rcec_all() Li Ming
2024-03-25 20:15 ` Terry Bowman
2024-04-16 4:39 ` Dan Williams
2024-04-22 14:34 ` Terry Bowman
2024-04-22 23:03 ` Dan Williams
2024-04-23 2:33 ` Li, Ming
2024-04-16 7:23 ` Li, Ming
2024-03-13 8:35 ` [RFC PATCH 2/6] PCI/CXL: A new attribute to indicate CXL-capable host bridge Li Ming
2024-03-13 8:35 ` [RFC PATCH 3/6] PCI/AER: Enable RCEC to report internal error for CXL root port Li Ming
2024-03-25 19:42 ` Terry Bowman
2024-04-16 7:27 ` Li, Ming
2024-04-16 14:46 ` Terry Bowman
2024-04-18 5:53 ` Li, Ming
2024-04-18 14:57 ` Dan Williams
2024-04-22 2:06 ` Li, Ming
2024-04-22 23:01 ` Dan Williams
2024-03-13 8:36 ` [RFC PATCH 4/6] PCI/AER: Extend RCH RAS error handling to support VH topology case Li Ming
2024-03-15 2:30 ` Dan Williams
2024-03-15 3:43 ` Li, Ming
2024-03-15 4:05 ` Dan Williams
2024-03-15 5:08 ` Li, Ming
2024-03-25 19:14 ` Terry Bowman
2024-03-13 8:36 ` Li Ming [this message]
2024-03-15 2:24 ` [RFC PATCH 5/6] cxl: Use __free() for cxl_pci/mem_find_port() to drop put_device() Dan Williams
2024-03-15 4:05 ` Li, Ming
2024-03-13 8:36 ` [RFC PATCH 6/6] cxl/pci: Support to handle root port RAS errors captured by RCEC Li Ming
2024-03-15 1:45 ` [RFC PATCH 0/6] Add support for root port RAS error handling Dan Williams
2024-03-15 8:40 ` Li, Ming
2024-03-15 18:21 ` Dan Williams
2024-03-20 12:48 ` Li, Ming
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