[PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

[PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

[Joshua Yeong]

StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
conventional CMO method. This driver provides the cache handling on StarFive
RISC-V SoC.

Joshua Yeong (4):
  riscv: asm: vendorid_list: Add StarFive Technology to vendors list
  riscv: errata: Add StarFive alternative ports
  cache: Add StarLink-500 cache management for StarFive  JH8100 RISC-V
    core
  dt-bindings: cache: Add docs for StarFive StarLink-500 cache
    controller

 .../cache/starfive,starlink-500-cache.yaml    |  62 ++++++++
 arch/riscv/Kconfig.errata                     |  21 +++
 arch/riscv/errata/Makefile                    |   1 +
 arch/riscv/errata/starfive/Makefile           |   1 +
 arch/riscv/errata/starfive/errata.c           |  95 ++++++++++++
 arch/riscv/include/asm/alternative.h          |   3 +
 arch/riscv/include/asm/errata_list.h          |   5 +
 arch/riscv/include/asm/vendorid_list.h        |   1 +
 arch/riscv/kernel/alternative.c               |   5 +
 drivers/cache/Kconfig                         |   9 ++
 drivers/cache/Makefile                        |   1 +
 drivers/cache/starlink500_cache.c             | 137 ++++++++++++++++++
 12 files changed, 341 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
 create mode 100644 arch/riscv/errata/starfive/Makefile
 create mode 100644 arch/riscv/errata/starfive/errata.c
 create mode 100644 drivers/cache/starlink500_cache.c

--
2.25.1

[PATCH 1/4] riscv: asm: vendorid_list: Add StarFive Technology to vendors list

[Joshua Yeong]

Add StarFive Technology to the vendors list.

Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
 arch/riscv/include/asm/vendorid_list.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index e55407ace0c3..8c8f19ea505f 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -7,6 +7,7 @@
 
 #define ANDESTECH_VENDOR_ID	0x31e
 #define SIFIVE_VENDOR_ID	0x489
+#define STARFIVE_VENDOR_ID	0x67e
 #define THEAD_VENDOR_ID		0x5b7
 
 #endif
-- 
2.25.1

[PATCH 2/4] riscv: errata: Add StarFive alternative ports

[Joshua Yeong]

Add required ports of the Alternative scheme for
StarFive CPU cores.

Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
 arch/riscv/Kconfig.errata            | 21 ++++++
 arch/riscv/errata/Makefile           |  1 +
 arch/riscv/errata/starfive/Makefile  |  1 +
 arch/riscv/errata/starfive/errata.c  | 95 ++++++++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h |  3 +
 arch/riscv/include/asm/errata_list.h |  5 ++
 arch/riscv/kernel/alternative.c      |  5 ++
 7 files changed, 131 insertions(+)
 create mode 100644 arch/riscv/errata/starfive/Makefile
 create mode 100644 arch/riscv/errata/starfive/errata.c

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 910ba8837add..1438dd09533b 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -53,6 +53,16 @@ config ERRATA_SIFIVE_CIP_1200
 
 	  If you don't know what to do here, say "Y".
 
+config ERRATA_STARFIVE
+	bool "StarFive errata"
+	depends on RISCV_ALTERNATIVE
+	help
+	  All StarFive errata Kconfig depend on this Kconfig. Disabling
+	  this Kconfig will disable all StarFive errata. Please say "Y"
+	  here if your platform uses StarFive CPU cores.
+
+	  Otherwise, please say "N" here to avoid unnecessary overhead.
+
 config ERRATA_STARFIVE_JH7100
 	bool "StarFive JH7100 support"
 	depends on ARCH_STARFIVE
@@ -72,6 +82,17 @@ config ERRATA_STARFIVE_JH7100
 	  Say "Y" if you want to support the BeagleV Starlight and/or
 	  StarFive VisionFive V1 boards.
 
+config ERRATA_STARFIVE_CMO
+	bool "Apply StarFive cache management errata"
+	depends on ERRATA_STARFIVE && MMU
+	select RISCV_DMA_NONCOHERENT
+	default y
+	help
+	  This will apply the cache management errata to handle the
+	  non-standard handling on non-coherent operations on StarFive cores.
+
+	  If you don't know what to do here, say "Y".
+
 config ERRATA_THEAD
 	bool "T-HEAD errata"
 	depends on RISCV_ALTERNATIVE
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index 8a2739485123..4713a686b9f7 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -4,4 +4,5 @@ endif
 
 obj-$(CONFIG_ERRATA_ANDES) += andes/
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
+obj-$(CONFIG_ERRATA_STARFIVE) += starfive/
 obj-$(CONFIG_ERRATA_THEAD) += thead/
diff --git a/arch/riscv/errata/starfive/Makefile b/arch/riscv/errata/starfive/Makefile
new file mode 100644
index 000000000000..2d644e19caef
--- /dev/null
+++ b/arch/riscv/errata/starfive/Makefile
@@ -0,0 +1 @@
+obj-y += errata.o
diff --git a/arch/riscv/errata/starfive/errata.c b/arch/riscv/errata/starfive/errata.c
new file mode 100644
index 000000000000..3ee360cd5e81
--- /dev/null
+++ b/arch/riscv/errata/starfive/errata.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Erratas to be applied for StarFive CPU cores
+ *
+ * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
+ *
+ * Author: Joshua Yeong <joshua.yeong@starfivetech.com>
+ */
+
+#include <linux/memory.h>
+#include <linux/module.h>
+
+#include <asm/alternative.h>
+#include <asm/cacheflush.h>
+#include <asm/errata_list.h>
+#include <asm/patch.h>
+#include <asm/processor.h>
+#include <asm/sbi.h>
+#include <asm/vendorid_list.h>
+
+#define STARFIVE_JH8100_DUBHE90_MARCHID	0x80000000DB000090UL
+#define STARFIVE_JH8100_DUBHE90_MIMPID	0x0000000020230930UL
+#define STARFIVE_JH8100_DUBHE80_MARCHID	0x80000000DB000080UL
+#define STARFIVE_JH8100_DUBHE80_MIMPID	0x0000000020230831UL
+#define STARFIVE_JH8100_L3		0x40
+
+static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id,
+			      unsigned long impid)
+{
+	if (!IS_ENABLED(CONFIG_ERRATA_STARFIVE_CMO))
+		return false;
+
+	if ((arch_id != STARFIVE_JH8100_DUBHE90_MARCHID ||
+	    impid != STARFIVE_JH8100_DUBHE90_MIMPID) &&
+	    (arch_id != STARFIVE_JH8100_DUBHE80_MARCHID ||
+	    impid != STARFIVE_JH8100_DUBHE80_MIMPID))
+		return false;
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return false;
+
+	riscv_cbom_block_size = STARFIVE_JH8100_L3;
+	riscv_noncoherent_supported();
+
+	return true;
+}
+
+static u32 starfive_errata_probe(unsigned int stage,
+			      unsigned long archid, unsigned long impid)
+{
+	u32 cpu_req_errata = 0;
+
+	if (errata_probe_cmo(stage, archid, impid))
+		cpu_req_errata |= BIT(ERRATA_STARFIVE_CMO);
+
+	return cpu_req_errata;
+}
+
+void __init_or_module starfive_errata_patch_func(struct alt_entry *begin,
+					         struct alt_entry *end,
+					         unsigned long archid,
+						 unsigned long impid,
+						 unsigned int stage)
+{
+	struct alt_entry *alt;
+	u32 cpu_apply_errata = 0;
+	u32 tmp;
+	u32 cpu_req_errata;
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return;
+
+	cpu_req_errata = starfive_errata_probe(stage, archid, impid);
+
+	for (alt = begin; alt < end; alt++) {
+		if (alt->vendor_id != STARFIVE_VENDOR_ID)
+			continue;
+		if (alt->patch_id >= ERRATA_STARFIVE_NUMBER)
+			continue;
+
+		tmp = (1U << alt->patch_id);
+		if (cpu_req_errata & tmp) {
+			mutex_lock(&text_mutex);
+			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
+					  alt->alt_len);
+			mutex_unlock(&text_mutex);
+			cpu_apply_errata |= tmp;
+		}
+	}
+
+	if (stage != RISCV_ALTERNATIVES_MODULE &&
+	    cpu_apply_errata != cpu_req_errata) {
+		pr_warn("WARNING: Missing StarFive errata patches! \n");
+	    }
+}
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index 3c2b59b25017..8f5e6883db97 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -51,6 +51,9 @@ void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
+void starfive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+			     unsigned long archid, unsigned long impid,
+			     unsigned int stage);
 void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			     unsigned long archid, unsigned long impid,
 			     unsigned int stage);
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index ea33288f8a25..1cd5ba3a1466 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -22,6 +22,11 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
+#ifdef CONFIG_ERRATA_STARFIVE
+#define	ERRATA_STARFIVE_CMO 0
+#define	ERRATA_STARFIVE_NUMBER 1
+#endif
+
 #ifdef CONFIG_ERRATA_THEAD
 #define	ERRATA_THEAD_PBMT 0
 #define	ERRATA_THEAD_PMU 1
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 319a1da0358b..deedd4b76472 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -52,6 +52,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
 		cpu_mfr_info->patch_func = sifive_errata_patch_func;
 		break;
 #endif
+#ifdef CONFIG_ERRATA_STARFIVE
+	case STARFIVE_VENDOR_ID:
+		cpu_mfr_info->patch_func = starfive_errata_patch_func;
+		break;
+#endif
 #ifdef CONFIG_ERRATA_THEAD
 	case THEAD_VENDOR_ID:
 		cpu_mfr_info->patch_func = thead_errata_patch_func;
-- 
2.25.1

Re: [PATCH 2/4] riscv: errata: Add StarFive alternative ports

[Samuel Holland]

On 2024-03-14 1:12 AM, Joshua Yeong wrote:
> Add required ports of the Alternative scheme for
> StarFive CPU cores.
> 
> Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> ---
>  arch/riscv/Kconfig.errata            | 21 ++++++
>  arch/riscv/errata/Makefile           |  1 +
>  arch/riscv/errata/starfive/Makefile  |  1 +
>  arch/riscv/errata/starfive/errata.c  | 95 ++++++++++++++++++++++++++++
>  arch/riscv/include/asm/alternative.h |  3 +
>  arch/riscv/include/asm/errata_list.h |  5 ++
>  arch/riscv/kernel/alternative.c      |  5 ++
>  7 files changed, 131 insertions(+)
>  create mode 100644 arch/riscv/errata/starfive/Makefile
>  create mode 100644 arch/riscv/errata/starfive/errata.c
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 910ba8837add..1438dd09533b 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -53,6 +53,16 @@ config ERRATA_SIFIVE_CIP_1200
>  
>  	  If you don't know what to do here, say "Y".
>  
> +config ERRATA_STARFIVE
> +	bool "StarFive errata"
> +	depends on RISCV_ALTERNATIVE
> +	help
> +	  All StarFive errata Kconfig depend on this Kconfig. Disabling
> +	  this Kconfig will disable all StarFive errata. Please say "Y"
> +	  here if your platform uses StarFive CPU cores.
> +
> +	  Otherwise, please say "N" here to avoid unnecessary overhead.
> +
>  config ERRATA_STARFIVE_JH7100
>  	bool "StarFive JH7100 support"
>  	depends on ARCH_STARFIVE
> @@ -72,6 +82,17 @@ config ERRATA_STARFIVE_JH7100
>  	  Say "Y" if you want to support the BeagleV Starlight and/or
>  	  StarFive VisionFive V1 boards.
>  
> +config ERRATA_STARFIVE_CMO
> +	bool "Apply StarFive cache management errata"
> +	depends on ERRATA_STARFIVE && MMU
> +	select RISCV_DMA_NONCOHERENT
> +	default y
> +	help
> +	  This will apply the cache management errata to handle the
> +	  non-standard handling on non-coherent operations on StarFive cores.
> +
> +	  If you don't know what to do here, say "Y".
> +
>  config ERRATA_THEAD
>  	bool "T-HEAD errata"
>  	depends on RISCV_ALTERNATIVE
> diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
> index 8a2739485123..4713a686b9f7 100644
> --- a/arch/riscv/errata/Makefile
> +++ b/arch/riscv/errata/Makefile
> @@ -4,4 +4,5 @@ endif
>  
>  obj-$(CONFIG_ERRATA_ANDES) += andes/
>  obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
> +obj-$(CONFIG_ERRATA_STARFIVE) += starfive/
>  obj-$(CONFIG_ERRATA_THEAD) += thead/
> diff --git a/arch/riscv/errata/starfive/Makefile b/arch/riscv/errata/starfive/Makefile
> new file mode 100644
> index 000000000000..2d644e19caef
> --- /dev/null
> +++ b/arch/riscv/errata/starfive/Makefile
> @@ -0,0 +1 @@
> +obj-y += errata.o
> diff --git a/arch/riscv/errata/starfive/errata.c b/arch/riscv/errata/starfive/errata.c
> new file mode 100644
> index 000000000000..3ee360cd5e81
> --- /dev/null
> +++ b/arch/riscv/errata/starfive/errata.c
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Erratas to be applied for StarFive CPU cores
> + *
> + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
> + *
> + * Author: Joshua Yeong <joshua.yeong@starfivetech.com>
> + */
> +
> +#include <linux/memory.h>
> +#include <linux/module.h>
> +
> +#include <asm/alternative.h>
> +#include <asm/cacheflush.h>
> +#include <asm/errata_list.h>
> +#include <asm/patch.h>
> +#include <asm/processor.h>
> +#include <asm/sbi.h>
> +#include <asm/vendorid_list.h>
> +
> +#define STARFIVE_JH8100_DUBHE90_MARCHID	0x80000000DB000090UL
> +#define STARFIVE_JH8100_DUBHE90_MIMPID	0x0000000020230930UL
> +#define STARFIVE_JH8100_DUBHE80_MARCHID	0x80000000DB000080UL
> +#define STARFIVE_JH8100_DUBHE80_MIMPID	0x0000000020230831UL
> +#define STARFIVE_JH8100_L3		0x40
> +
> +static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id,
> +			      unsigned long impid)
> +{
> +	if (!IS_ENABLED(CONFIG_ERRATA_STARFIVE_CMO))
> +		return false;
> +
> +	if ((arch_id != STARFIVE_JH8100_DUBHE90_MARCHID ||
> +	    impid != STARFIVE_JH8100_DUBHE90_MIMPID) &&
> +	    (arch_id != STARFIVE_JH8100_DUBHE80_MARCHID ||
> +	    impid != STARFIVE_JH8100_DUBHE80_MIMPID))
> +		return false;
> +
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return false;
> +
> +	riscv_cbom_block_size = STARFIVE_JH8100_L3;
> +	riscv_noncoherent_supported();

This patch doesn't add any alternatives, so you don't need to use the errata
framework. Please move these two lines to the cache driver -- see
drivers/cache/sifive_ccache.c -- and then you can drop this patch.

Regards,
Samuel

> +
> +	return true;
> +}
> +
> +static u32 starfive_errata_probe(unsigned int stage,
> +			      unsigned long archid, unsigned long impid)
> +{
> +	u32 cpu_req_errata = 0;
> +
> +	if (errata_probe_cmo(stage, archid, impid))
> +		cpu_req_errata |= BIT(ERRATA_STARFIVE_CMO);
> +
> +	return cpu_req_errata;
> +}
> +
> +void __init_or_module starfive_errata_patch_func(struct alt_entry *begin,
> +					         struct alt_entry *end,
> +					         unsigned long archid,
> +						 unsigned long impid,
> +						 unsigned int stage)
> +{
> +	struct alt_entry *alt;
> +	u32 cpu_apply_errata = 0;
> +	u32 tmp;
> +	u32 cpu_req_errata;
> +
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return;
> +
> +	cpu_req_errata = starfive_errata_probe(stage, archid, impid);
> +
> +	for (alt = begin; alt < end; alt++) {
> +		if (alt->vendor_id != STARFIVE_VENDOR_ID)
> +			continue;
> +		if (alt->patch_id >= ERRATA_STARFIVE_NUMBER)
> +			continue;
> +
> +		tmp = (1U << alt->patch_id);
> +		if (cpu_req_errata & tmp) {
> +			mutex_lock(&text_mutex);
> +			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
> +					  alt->alt_len);
> +			mutex_unlock(&text_mutex);
> +			cpu_apply_errata |= tmp;
> +		}
> +	}
> +
> +	if (stage != RISCV_ALTERNATIVES_MODULE &&
> +	    cpu_apply_errata != cpu_req_errata) {
> +		pr_warn("WARNING: Missing StarFive errata patches! \n");
> +	    }
> +}
> diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
> index 3c2b59b25017..8f5e6883db97 100644
> --- a/arch/riscv/include/asm/alternative.h
> +++ b/arch/riscv/include/asm/alternative.h
> @@ -51,6 +51,9 @@ void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>  void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>  			      unsigned long archid, unsigned long impid,
>  			      unsigned int stage);
> +void starfive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> +			     unsigned long archid, unsigned long impid,
> +			     unsigned int stage);
>  void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>  			     unsigned long archid, unsigned long impid,
>  			     unsigned int stage);
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index ea33288f8a25..1cd5ba3a1466 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -22,6 +22,11 @@
>  #define	ERRATA_SIFIVE_NUMBER 2
>  #endif
>  
> +#ifdef CONFIG_ERRATA_STARFIVE
> +#define	ERRATA_STARFIVE_CMO 0
> +#define	ERRATA_STARFIVE_NUMBER 1
> +#endif
> +
>  #ifdef CONFIG_ERRATA_THEAD
>  #define	ERRATA_THEAD_PBMT 0
>  #define	ERRATA_THEAD_PMU 1
> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> index 319a1da0358b..deedd4b76472 100644
> --- a/arch/riscv/kernel/alternative.c
> +++ b/arch/riscv/kernel/alternative.c
> @@ -52,6 +52,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
>  		cpu_mfr_info->patch_func = sifive_errata_patch_func;
>  		break;
>  #endif
> +#ifdef CONFIG_ERRATA_STARFIVE
> +	case STARFIVE_VENDOR_ID:
> +		cpu_mfr_info->patch_func = starfive_errata_patch_func;
> +		break;
> +#endif
>  #ifdef CONFIG_ERRATA_THEAD
>  	case THEAD_VENDOR_ID:
>  		cpu_mfr_info->patch_func = thead_errata_patch_func;

Re: [PATCH 2/4] riscv: errata: Add StarFive alternative ports

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 467 bytes --]

On Fri, Mar 15, 2024 at 06:13:34PM -0500, Samuel Holland wrote:
> > +	riscv_cbom_block_size = STARFIVE_JH8100_L3;
> > +	riscv_noncoherent_supported();
> 
> This patch doesn't add any alternatives, so you don't need to use the errata
> framework. Please move these two lines to the cache driver -- see
> drivers/cache/sifive_ccache.c -- and then you can drop this patch.

And drop the patch adding the vendor ID too I guess, since that'll no
longer be used.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH 3/4] cache: Add StarLink-500 cache management for StarFive JH8100 RISC-V core

[Joshua Yeong]

Add software workaround for StarFive StarLink-500
on JH8100 SoC for CMO extension instructions.

Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
 drivers/cache/Kconfig             |   9 ++
 drivers/cache/Makefile            |   1 +
 drivers/cache/starlink500_cache.c | 137 ++++++++++++++++++++++++++++++
 3 files changed, 147 insertions(+)
 create mode 100644 drivers/cache/starlink500_cache.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 9345ce4976d7..e215379f6a73 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -14,4 +14,13 @@ config SIFIVE_CCACHE
 	help
 	  Support for the composable cache controller on SiFive platforms.
 
+config STARLINK_500_CACHE
+	bool "StarLink-500 Cache controller"
+	depends on RISCV_DMA_NONCOHERENT
+	depends on ERRATA_STARFIVE
+	select RISCV_NONSTANDARD_CACHE_OPS
+	default y
+	help
+	  Support for the StarLink-500 cache controller on StarFive platforms.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 7657cff3bd6c..c515eb5714ea 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_AX45MP_L2_CACHE)	+= ax45mp_cache.o
 obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o
+obj-$(CONFIG_STARLINK_500_CACHE) += starlink500_cache.o
diff --git a/drivers/cache/starlink500_cache.c b/drivers/cache/starlink500_cache.c
new file mode 100644
index 000000000000..eaf8303cb086
--- /dev/null
+++ b/drivers/cache/starlink500_cache.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Non-coherent cache functions for StarFive's StarLink-500 cache controller
+ *
+ * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
+ *
+ * Author: Joshua Yeong <joshua.yeong@starfivetech.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cacheflush.h>
+#include <linux/cacheinfo.h>
+#include <linux/delay.h>
+#include <linux/dma-direction.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/processor.h>
+
+#include <asm/dma-noncoherent.h>
+
+#define STARFIVE_SL500_CMO_FLUSH_START_ADDR		0x0
+#define STARFIVE_SL500_CMO_FLUSH_END_ADDR		0x8
+#define STARFIVE_SL500_CMO_FLUSH_CTL			0x10
+#define STARFIVE_SL500_CMO_CACHE_ALIGN			0x40
+
+#define STARFIVE_SL500_ADDRESS_RANGE_MASK		GENMASK(39, 0)
+#define STARFIVE_SL500_FLUSH_CTL_MODE_MASK		GENMASK(2, 1)
+#define STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK		BIT(0)
+
+#define STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE	0
+#define STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE	1
+#define STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED		2
+
+struct starfive_sl500_cache_priv {
+	void __iomem *base_addr;
+};
+
+static struct starfive_sl500_cache_priv starfive_sl500_cache_priv;
+
+static void starfive_sl500_cmo_flush_complete(void)
+{
+	ktime_t timeout;
+
+	volatile void __iomem *_ctl = starfive_sl500_cache_priv.base_addr +
+                                      STARFIVE_SL500_CMO_FLUSH_CTL;
+	timeout = ktime_add_ms(ktime_get(), 5000);
+
+	do {
+		if(!(ioread64(_ctl) & STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK))
+			return;
+		msleep(50);
+	} while (ktime_before(ktime_get(), timeout));
+
+	pr_err("StarFive CMO operation timeout\n");
+	dump_stack();
+}
+
+void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size)
+{
+	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
+	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
+
+	mb();
+	writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
+	       STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
+
+	starfive_sl500_cmo_flush_complete();
+}
+
+void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
+{
+	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
+	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
+
+	mb();
+	writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
+	       STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
+
+	starfive_sl500_cmo_flush_complete();
+}
+
+void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
+{
+	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
+	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
+
+	mb();
+	writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
+	       STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE),
+	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
+
+	starfive_sl500_cmo_flush_complete();
+}
+
+static const struct riscv_nonstd_cache_ops starfive_sl500_cmo_ops = {
+	.wback = &starfive_sl500_dma_cache_wback,
+	.inv = &starfive_sl500_dma_cache_invalidate,
+	.wback_inv = &starfive_sl500_dma_cache_wback_inv,
+};
+
+static const struct of_device_id starfive_sl500_cache_ids[] = {
+	{ .compatible = "starfive,starlink-500-cache" },
+	{ /* sentinel */ }
+};
+
+static int __init starfive_sl500_cache_init(void)
+{
+	struct device_node *np;
+	struct resource res;
+	int ret;
+
+	np = of_find_matching_node(NULL, starfive_sl500_cache_ids);
+	if (!of_device_is_available(np))
+		return -ENODEV;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return ret;
+
+	starfive_sl500_cache_priv.base_addr = ioremap(res.start, resource_size(&res));
+	if (!starfive_sl500_cache_priv.base_addr)
+		return -ENOMEM;
+
+	riscv_noncoherent_register_cache_ops(&starfive_sl500_cmo_ops);
+
+	return 0;
+}
+early_initcall(starfive_sl500_cache_init);
-- 
2.25.1

Re: [PATCH 3/4] cache: Add StarLink-500 cache management for StarFive JH8100 RISC-V core

[kernel test robot]

Hi Joshua,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.8 next-20240314]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Joshua-Yeong/riscv-asm-vendorid_list-Add-StarFive-Technology-to-vendors-list/20240314-165125
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20240314061205.26143-4-joshua.yeong%40starfivetech.com
patch subject: [PATCH 3/4] cache: Add StarLink-500 cache management for StarFive  JH8100 RISC-V core
config: riscv-allmodconfig (https://download.01.org/0day-ci/archive/20240315/202403151625.boKDjHGr-lkp@intel.com/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project 8f68022f8e6e54d1aeae4ed301f5a015963089b7)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240315/202403151625.boKDjHGr-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403151625.boKDjHGr-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/cache/starlink500_cache.c:11:
   In file included from include/linux/cacheflush.h:5:
   In file included from arch/riscv/include/asm/cacheflush.h:9:
   In file included from include/linux/mm.h:2188:
   include/linux/vmstat.h:508:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     508 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     509 |                            item];
         |                            ~~~~
   include/linux/vmstat.h:515:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     515 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     516 |                            NR_VM_NUMA_EVENT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~~
   include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
     522 |         return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
         |                               ~~~~~~~~~~~ ^ ~~~
   include/linux/vmstat.h:527:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     527 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     528 |                            NR_VM_NUMA_EVENT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~~
   include/linux/vmstat.h:536:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     536 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     537 |                            NR_VM_NUMA_EVENT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~~
>> drivers/cache/starlink500_cache.c:59:6: warning: no previous prototype for function 'starfive_sl500_dma_cache_wback' [-Wmissing-prototypes]
      59 | void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size)
         |      ^
   drivers/cache/starlink500_cache.c:59:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
      59 | void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size)
         | ^
         | static 
>> drivers/cache/starlink500_cache.c:74:6: warning: no previous prototype for function 'starfive_sl500_dma_cache_invalidate' [-Wmissing-prototypes]
      74 | void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
         |      ^
   drivers/cache/starlink500_cache.c:74:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
      74 | void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
         | ^
         | static 
>> drivers/cache/starlink500_cache.c:89:6: warning: no previous prototype for function 'starfive_sl500_dma_cache_wback_inv' [-Wmissing-prototypes]
      89 | void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
         |      ^
   drivers/cache/starlink500_cache.c:89:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
      89 | void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
         | ^
         | static 
   8 warnings generated.


vim +/starfive_sl500_dma_cache_wback +59 drivers/cache/starlink500_cache.c

    58	
  > 59	void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size)
    60	{
    61		writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
    62		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
    63		writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
    64		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
    65	
    66		mb();
    67		writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
    68		       STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED),
    69		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
    70	
    71		starfive_sl500_cmo_flush_complete();
    72	}
    73	
  > 74	void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
    75	{
    76		writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
    77		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
    78		writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
    79		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
    80	
    81		mb();
    82		writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
    83		       STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE),
    84		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
    85	
    86		starfive_sl500_cmo_flush_complete();
    87	}
    88	
  > 89	void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
    90	{
    91		writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
    92		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
    93		writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
    94		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
    95	
    96		mb();
    97		writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
    98		       STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE),
    99		       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
   100	
   101		starfive_sl500_cmo_flush_complete();
   102	}
   103	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 3/4] cache: Add StarLink-500 cache management for StarFive JH8100 RISC-V core

[Samuel Holland]

On 2024-03-14 1:12 AM, Joshua Yeong wrote:
> Add software workaround for StarFive StarLink-500
> on JH8100 SoC for CMO extension instructions.
> 
> Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> ---
>  drivers/cache/Kconfig             |   9 ++
>  drivers/cache/Makefile            |   1 +
>  drivers/cache/starlink500_cache.c | 137 ++++++++++++++++++++++++++++++
>  3 files changed, 147 insertions(+)
>  create mode 100644 drivers/cache/starlink500_cache.c
> 
> diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> index 9345ce4976d7..e215379f6a73 100644
> --- a/drivers/cache/Kconfig
> +++ b/drivers/cache/Kconfig
> @@ -14,4 +14,13 @@ config SIFIVE_CCACHE
>  	help
>  	  Support for the composable cache controller on SiFive platforms.
>  
> +config STARLINK_500_CACHE
> +	bool "StarLink-500 Cache controller"
> +	depends on RISCV_DMA_NONCOHERENT
> +	depends on ERRATA_STARFIVE
> +	select RISCV_NONSTANDARD_CACHE_OPS
> +	default y
> +	help
> +	  Support for the StarLink-500 cache controller on StarFive platforms.
> +
>  endmenu
> diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> index 7657cff3bd6c..c515eb5714ea 100644
> --- a/drivers/cache/Makefile
> +++ b/drivers/cache/Makefile
> @@ -2,3 +2,4 @@
>  
>  obj-$(CONFIG_AX45MP_L2_CACHE)	+= ax45mp_cache.o
>  obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o
> +obj-$(CONFIG_STARLINK_500_CACHE) += starlink500_cache.o
> diff --git a/drivers/cache/starlink500_cache.c b/drivers/cache/starlink500_cache.c
> new file mode 100644
> index 000000000000..eaf8303cb086
> --- /dev/null
> +++ b/drivers/cache/starlink500_cache.c
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Non-coherent cache functions for StarFive's StarLink-500 cache controller
> + *
> + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
> + *
> + * Author: Joshua Yeong <joshua.yeong@starfivetech.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/cacheflush.h>
> +#include <linux/cacheinfo.h>
> +#include <linux/delay.h>
> +#include <linux/dma-direction.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/processor.h>
> +
> +#include <asm/dma-noncoherent.h>
> +
> +#define STARFIVE_SL500_CMO_FLUSH_START_ADDR		0x0
> +#define STARFIVE_SL500_CMO_FLUSH_END_ADDR		0x8
> +#define STARFIVE_SL500_CMO_FLUSH_CTL			0x10
> +#define STARFIVE_SL500_CMO_CACHE_ALIGN			0x40
> +
> +#define STARFIVE_SL500_ADDRESS_RANGE_MASK		GENMASK(39, 0)
> +#define STARFIVE_SL500_FLUSH_CTL_MODE_MASK		GENMASK(2, 1)
> +#define STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK		BIT(0)
> +
> +#define STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE	0
> +#define STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE	1
> +#define STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED		2
> +
> +struct starfive_sl500_cache_priv {
> +	void __iomem *base_addr;
> +};
> +
> +static struct starfive_sl500_cache_priv starfive_sl500_cache_priv;
> +
> +static void starfive_sl500_cmo_flush_complete(void)
> +{
> +	ktime_t timeout;
> +
> +	volatile void __iomem *_ctl = starfive_sl500_cache_priv.base_addr +
> +                                      STARFIVE_SL500_CMO_FLUSH_CTL;
> +	timeout = ktime_add_ms(ktime_get(), 5000);
> +
> +	do {
> +		if(!(ioread64(_ctl) & STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK))
> +			return;
> +		msleep(50);

These callbacks can be called from an atomic context, so you cannot use msleep()
here.

> +	} while (ktime_before(ktime_get(), timeout));

I suggest using one of the helpers from linux/iopoll.h, e.g. readq_poll_timeout().

> +
> +	pr_err("StarFive CMO operation timeout\n");
> +	dump_stack();

WARN or WARN_ON would be idiomatic here.

> +}
> +
> +void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size)
> +{
> +	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
> +	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
> +
> +	mb();
> +	writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
> +	       STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
> +
> +	starfive_sl500_cmo_flush_complete();
> +}
> +
> +void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
> +{
> +	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
> +	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
> +
> +	mb();
> +	writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
> +	       STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
> +
> +	starfive_sl500_cmo_flush_complete();
> +}
> +
> +void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
> +{
> +	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR);
> +	writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR);
> +
> +	mb();
> +	writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK,
> +	       STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE),
> +	       starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL);
> +
> +	starfive_sl500_cmo_flush_complete();
> +}
> +
> +static const struct riscv_nonstd_cache_ops starfive_sl500_cmo_ops = {
> +	.wback = &starfive_sl500_dma_cache_wback,
> +	.inv = &starfive_sl500_dma_cache_invalidate,
> +	.wback_inv = &starfive_sl500_dma_cache_wback_inv,
> +};
> +
> +static const struct of_device_id starfive_sl500_cache_ids[] = {
> +	{ .compatible = "starfive,starlink-500-cache" },
> +	{ /* sentinel */ }
> +};
> +
> +static int __init starfive_sl500_cache_init(void)
> +{
> +	struct device_node *np;
> +	struct resource res;
> +	int ret;
> +
> +	np = of_find_matching_node(NULL, starfive_sl500_cache_ids);
> +	if (!of_device_is_available(np))
> +		return -ENODEV;
> +
> +	ret = of_address_to_resource(np, 0, &res);
> +	if (ret)
> +		return ret;
> +
> +	starfive_sl500_cache_priv.base_addr = ioremap(res.start, resource_size(&res));
> +	if (!starfive_sl500_cache_priv.base_addr)
> +		return -ENOMEM;

of_address_to_resource() + ioremap() simplifies to of_iomap().

Regards,
Samuel

> +
> +	riscv_noncoherent_register_cache_ops(&starfive_sl500_cmo_ops);
> +
> +	return 0;
> +}
> +early_initcall(starfive_sl500_cache_init);

[PATCH 4/4] dt-bindings: cache: Add docs for StarFive StarLink-500 cache controller

[Joshua Yeong]

Add DT binding documentation used by StarFive's
Starlink-500 cache controller.

Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
 .../cache/starfive,starlink-500-cache.yaml    | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml

diff --git a/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
new file mode 100644
index 000000000000..97ddf7db39e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive StarLink-500 Cache Controller
+
+maintainers:
+  - Joshua Yeong <joshua.yeong@starfivetech.com>
+
+description:
+  StarFive's StarLink-500 controller manages cache shared between clusters of
+  CPU cores. The cache driver provides mechanism to perform invalidate and write
+  back functionality to the shared memory.
+
+allOf:
+  - $ref: /schemas/cache-controller.yaml#
+
+# We need a select here so we don't match all nodes with 'cache'
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - starfive,starlink-500-cache
+
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - const: starfive,starlink-500-cache
+      - const: cache
+
+  reg:
+    maxItems: 1
+
+  cache-size: true
+  cache-sets: true
+  cache-block-size: true
+  cache-level: true
+  cache-unified: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+      cache-controller@15000000 {
+        compatible = "starfive,starlink-500-cache", "cache";
+        reg = <0x15000000 0x278>;
+        cache-block-size = <64>;
+        cache-level = <3>;
+        cache-sets = <8192>;
+        cache-size = <0x400000>;
+        cache-unified;
+      };
-- 
2.25.1

Re: [PATCH 4/4] dt-bindings: cache: Add docs for StarFive StarLink-500 cache controller

[Rob Herring]

On Thu, Mar 14, 2024 at 02:12:05PM +0800, Joshua Yeong wrote:
> Add DT binding documentation used by StarFive's
> Starlink-500 cache controller.
> 
> Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> ---
>  .../cache/starfive,starlink-500-cache.yaml    | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
> 
> diff --git a/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
> new file mode 100644
> index 000000000000..97ddf7db39e9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive StarLink-500 Cache Controller
> +
> +maintainers:
> +  - Joshua Yeong <joshua.yeong@starfivetech.com>
> +
> +description:
> +  StarFive's StarLink-500 controller manages cache shared between clusters of
> +  CPU cores. The cache driver provides mechanism to perform invalidate and write
> +  back functionality to the shared memory.

What a driver does is not relevant to the binding. You could describe 
what the registers control though.

> +
> +allOf:
> +  - $ref: /schemas/cache-controller.yaml#
> +
> +# We need a select here so we don't match all nodes with 'cache'
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - starfive,starlink-500-cache
> +
> +  required:
> +    - compatible
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: starfive,starlink-500-cache
> +      - const: cache
> +
> +  reg:
> +    maxItems: 1
> +
> +  cache-size: true
> +  cache-sets: true
> +  cache-block-size: true
> +  cache-level: true
> +  cache-unified: true

Drop these and...

> +
> +additionalProperties: false

... use 'unevaluatedProperties' instead.

> +
> +required:
> +  - compatible
> +  - reg

cache-unified should be required as I imagine the cache is always 
unified. Perhaps other properties too (cache-level already is)?

> +
> +examples:
> +  - |
> +      cache-controller@15000000 {
> +        compatible = "starfive,starlink-500-cache", "cache";
> +        reg = <0x15000000 0x278>;
> +        cache-block-size = <64>;
> +        cache-level = <3>;
> +        cache-sets = <8192>;
> +        cache-size = <0x400000>;
> +        cache-unified;
> +      };
> -- 
> 2.25.1
> 

Re: [PATCH 4/4] dt-bindings: cache: Add docs for StarFive StarLink-500 cache controller

[Conor Dooley]

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On Fri, Mar 15, 2024 at 10:36:07AM -0600, Rob Herring wrote:
> On Thu, Mar 14, 2024 at 02:12:05PM +0800, Joshua Yeong wrote:
> > Add DT binding documentation used by StarFive's
> > Starlink-500 cache controller.
> > 
> > Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> > ---
> >  .../cache/starfive,starlink-500-cache.yaml    | 62 +++++++++++++++++++
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
> > new file mode 100644
> > index 000000000000..97ddf7db39e9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive StarLink-500 Cache Controller
> > +
> > +maintainers:
> > +  - Joshua Yeong <joshua.yeong@starfivetech.com>
> > +
> > +description:
> > +  StarFive's StarLink-500 controller manages cache shared between clusters of
> > +  CPU cores. The cache driver provides mechanism to perform invalidate and write
> > +  back functionality to the shared memory.
> 
> What a driver does is not relevant to the binding. You could describe 
> what the registers control though.
> 
> > +
> > +allOf:
> > +  - $ref: /schemas/cache-controller.yaml#
> > +
> > +# We need a select here so we don't match all nodes with 'cache'
> > +select:
> > +  properties:
> > +    compatible:
> > +      contains:
> > +        enum:
> > +          - starfive,starlink-500-cache
> > +
> > +  required:
> > +    - compatible
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: starfive,starlink-500-cache
> > +      - const: cache

You're also missing a soc-specific compatible here as far as I can tell,
as one of the other patches in this series specifically calls out the
JH8100 as where this cache controller is. AFAICT, "starlink-500" is the
name of the IP or of the coreplex - it's not the name of the SoC.

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  cache-size: true
> > +  cache-sets: true
> > +  cache-block-size: true
> > +  cache-level: true
> > +  cache-unified: true
> 
> Drop these and...
> 
> > +
> > +additionalProperties: false
> 
> ... use 'unevaluatedProperties' instead.
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> 
> cache-unified should be required as I imagine the cache is always 
> unified. Perhaps other properties too (cache-level already is)?

And I also suspect that a load of the values can be restricted to
specific values for that jh8100 compatible.

> 
> > +
> > +examples:
> > +  - |
> > +      cache-controller@15000000 {
> > +        compatible = "starfive,starlink-500-cache", "cache";
> > +        reg = <0x15000000 0x278>;
> > +        cache-block-size = <64>;
> > +        cache-level = <3>;
> > +        cache-sets = <8192>;
> > +        cache-size = <0x400000>;
> > +        cache-unified;
> > +      };
> > -- 
> > 2.25.1
> > 

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Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

[Conor Dooley]

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On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
> conventional CMO method. This driver provides the cache handling on StarFive
> RISC-V SoC.

Unlike the other "non-conventional" CMO methods, the jh8100 does not
pre-date the Zicbom extension. Why has that not been implemented?
How many peripherals on the jh8100 rely on non-coherent DMA?

Cheers,
Conor.

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Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

[Conor Dooley]

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On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
> > conventional CMO method. This driver provides the cache handling on StarFive
> > RISC-V SoC.
> 
> Unlike the other "non-conventional" CMO methods, the jh8100 does not
> pre-date the Zicbom extension. Why has that not been implemented?

Stefan pointed out on IRC yesterday that one of the main selling points
is the ease of operating on large ranges.

> How many peripherals on the jh8100 rely on non-coherent DMA?
> 
> Cheers,
> Conor.



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RE: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

[Joshua Yeong]

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor.dooley@microchip.com>
> Sent: Wednesday, March 20, 2024 4:09 PM
> To: Conor Dooley <conor@kernel.org>
> Cc: Joshua Yeong <joshua.yeong@starfivetech.com>;
> paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> geert+renesas@glider.be; prabhakar.mahadev-lad.rj@bp.renesas.com;
> alexghiti@rivosinc.com; evan@rivosinc.com; ajones@ventanamicro.com;
> heiko@sntech.de; guoren@kernel.org; uwu@icenowy.me;
> jszhang@kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; JeeHeng
> Sia <jeeheng.sia@starfivetech.com>; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
> 
> On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> > On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > > StarFive's StarLink-500 Cache Controller flush/invalidates cache
> > > using non- conventional CMO method. This driver provides the cache
> > > handling on StarFive RISC-V SoC.
> >
> > Unlike the other "non-conventional" CMO methods, the jh8100 does not
> > pre-date the Zicbom extension. Why has that not been implemented?
> 
> Stefan pointed out on IRC yesterday that one of the main selling points is the
> ease of operating on large ranges.
> 
> > How many peripherals on the jh8100 rely on non-coherent DMA?

JH8100 integrates in-house matured/stable CPU but it is a bit dated today.
However, our newer generation of CPU should already support this extension.

Most of the peripherals are coherent except mainly multimedia peripheral.

Regards,
Joshua

> >
> > Cheers,
> > Conor.
>