From: Ian Rogers <irogers@google.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Perry Taylor <perry.taylor@intel.com>,
Samantha Alt <samantha.alt@intel.com>,
Caleb Biggers <caleb.biggers@intel.com>,
Weilin Wang <weilin.wang@intel.com>,
Edward Baker <edward.baker@intel.com>
Subject: [PATCH v1 10/12] perf vendor events intel: Update skylake to v58
Date: Wed, 20 Mar 2024 23:00:14 -0700 [thread overview]
Message-ID: <20240321060016.1464787-11-irogers@google.com> (raw)
In-Reply-To: <20240321060016.1464787-1-irogers@google.com>
Update events from:
https://github.com/intel/perfmon/commit/f2e5136e062a91ae554dc40530132e66f9271848
This change didn't increase the version number from v58.
Updates various descriptions.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/skylake/frontend.json | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/perf/pmu-events/arch/x86/skylake/frontend.json
index 095904c77001..d6f543471b24 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json
@@ -19,7 +19,7 @@
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
- "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
+ "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
@@ -267,11 +267,11 @@
"UMask": "0x4"
},
{
- "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
+ "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
- "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
+ "PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
@@ -321,11 +321,11 @@
"UMask": "0x18"
},
{
- "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+ "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
- "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+ "PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
--
2.44.0.396.g6e790dbe36-goog
next prev parent reply other threads:[~2024-03-21 6:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-21 6:00 [PATCH v1 00/12] perf vendor events intel update Ian Rogers
2024-03-21 6:00 ` [PATCH v1 01/12] perf vendor events intel: Update cascadelakex to 1.21 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 02/12] perf vendor events intel: Update emeraldrapids to 1.06 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 03/12] perf vendor events intel: Update grandridge to 1.02 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 04/12] perf vendor events intel: Update icelakex to 1.24 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 05/12] perf vendor events intel: Update lunarlake to 1.01 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 06/12] perf vendor events intel: Update meteorlake to 1.08 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 07/12] perf vendor events intel: Update sapphirerapids to 1.20 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 08/12] perf vendor events intel: Update sierraforest to 1.02 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 09/12] perf vendor events intel: Update skylakex to 1.33 Ian Rogers
2024-03-21 6:00 ` Ian Rogers [this message]
2024-03-21 6:00 ` [PATCH v1 11/12] perf vendor events intel: Update snowridgex to 1.22 Ian Rogers
2024-03-21 6:00 ` [PATCH v1 12/12] perf vendor events intel: Remove info metrics erroneously in TopdownL1 Ian Rogers
2024-03-21 14:25 ` [PATCH v1 00/12] perf vendor events intel update Arnaldo Carvalho de Melo
2024-03-21 15:14 ` Liang, Kan
2024-03-21 15:23 ` Arnaldo Carvalho de Melo
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