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From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/5] riscv: nommu: remove PAGE_OFFSET hardcoding
Date: Tue, 26 Mar 2024 00:40:17 +0800	[thread overview]
Message-ID: <20240325164021.3229-2-jszhang@kernel.org> (raw)
In-Reply-To: <20240325164021.3229-1-jszhang@kernel.org>

Currently, PAGE_OFFSET is hardcoded as 0x8000_0000, it works fine since
there's only one nommu platform in the mainline. However, there are
many cases where the (S)DRAM base address isn't 0x8000_0000, so remove
the hardcoding value, and introduce DRAM_BASE which will be set by
users during configuring. DRAM_BASE is 0x8000_0000 by default.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/Kconfig | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7895c77545f1..afd51dbdc253 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -247,10 +247,16 @@ config MMU
 	  Select if you want MMU-based virtualised addressing space
 	  support by paged memory management. If unsure, say 'Y'.
 
+if !MMU
+config DRAM_BASE
+	hex '(S)DRAM Base Address'
+	default 0x80000000
+endif
+
 config PAGE_OFFSET
 	hex
 	default 0xC0000000 if 32BIT && MMU
-	default 0x80000000 if !MMU
+	default DRAM_BASE if !MMU
 	default 0xff60000000000000 if 64BIT
 
 config KASAN_SHADOW_OFFSET
-- 
2.43.0


  reply	other threads:[~2024-03-25 16:53 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-25 16:40 [PATCH 0/5] riscv: improve nommu and timer-clint Jisheng Zhang
2024-03-25 16:40 ` Jisheng Zhang [this message]
2024-03-25 22:46   ` [PATCH 1/5] riscv: nommu: remove PAGE_OFFSET hardcoding Bo Gan
2024-03-26  1:28     ` Jisheng Zhang
2024-03-26  2:32       ` Samuel Holland
2024-03-25 16:40 ` [PATCH 2/5] riscv: nommu: use CSR_TIME* for get_cycles* implementation Jisheng Zhang
2024-03-26  2:39   ` Samuel Holland
2024-03-26 16:29     ` Jisheng Zhang
2024-03-27  7:58       ` [External] " yunhui cui
2024-03-28 10:11       ` Jisheng Zhang
2024-03-25 16:40 ` [PATCH 3/5] clocksource/drivers/timer-clint: Remove clint_time_val Jisheng Zhang
2024-03-25 16:40 ` [PATCH 4/5] clocksource/drivers/timer-clint: Use get_cycles() Jisheng Zhang
2024-03-25 16:40 ` [PATCH 5/5] clocksource/drivers/timer-clint: Add T-Head C9xx clint support Jisheng Zhang
2024-03-25 16:50   ` Jisheng Zhang
2024-03-25 22:22   ` Bo Gan
2024-03-26  1:25     ` Jisheng Zhang
2024-03-26  1:31       ` Jisheng Zhang
2024-03-26 16:33         ` Jisheng Zhang
2024-03-27 22:53   ` kernel test robot

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