[PATCH v2 0/2] RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE

[PATCH v2 0/2] RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE

[Christoph Müllner]

Currently, the Linux kernel suffers from a boot regression when running
on the c906 QEMU emulation. Details have been reported here by Björn Töpel:
  https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg04766.html

The main issue is, that Linux enables MAEE for CPUs that have a T-Head
mvendorid but QEMU maintainers don't want to emulate a CPU that uses
reserved bits in PTEs. See also the following discussion for more
context:
  https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

This series renames "T-Head PBMT" to "MAEE" and only enables it if
the th.sxstatus.MAEE bit is set.

The th.sxstatus CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/pull/46

The QEMU patch to emulate th.sxstatus with MAEE not set is here:
  https://lore.kernel.org/all/20240329120427.684677-1-christoph.muellner@vrull.eu/

After applying the referenced QEMU patch, this patchset allows to
successfully boot a C906 QEMU system emulation ("-cpu thead-c906").

Christoph Müllner (2):
  riscv: thead: Rename T-Head PBMT to MAEE
  riscv: T-Head: Test availability bit before enabling MAEE errata

 arch/riscv/Kconfig.errata            |  8 ++++----
 arch/riscv/errata/thead/errata.c     | 22 ++++++++++++++--------
 arch/riscv/include/asm/errata_list.h | 20 ++++++++++----------
 3 files changed, 28 insertions(+), 22 deletions(-)

-- 
2.44.0

[PATCH v2 1/2] riscv: thead: Rename T-Head PBMT to MAEE

[Christoph Müllner]

T-Head's vendor extension to set page attributes has the name
MAEE (MMU address attribute extension).
Let's rename it, so it is clear what this referes to.

See also:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 arch/riscv/Kconfig.errata            |  8 ++++----
 arch/riscv/errata/thead/errata.c     |  8 ++++----
 arch/riscv/include/asm/errata_list.h | 20 ++++++++++----------
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 910ba8837add..2c24bef7e112 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -82,14 +82,14 @@ config ERRATA_THEAD
 
 	  Otherwise, please say "N" here to avoid unnecessary overhead.
 
-config ERRATA_THEAD_PBMT
-	bool "Apply T-Head memory type errata"
+config ERRATA_THEAD_MAEE
+	bool "Apply T-Head's MMU address attribute (MAEE)"
 	depends on ERRATA_THEAD && 64BIT && MMU
 	select RISCV_ALTERNATIVE_EARLY
 	default y
 	help
-	  This will apply the memory type errata to handle the non-standard
-	  memory type bits in page-table-entries on T-Head SoCs.
+	  This will apply the memory type errata to handle T-Head's MMU address
+	  attribute extension (MAEE).
 
 	  If you don't know what to do here, say "Y".
 
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index b1c410bbc1ae..8c8a8a4b0421 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -19,10 +19,10 @@
 #include <asm/patch.h>
 #include <asm/vendorid_list.h>
 
-static bool errata_probe_pbmt(unsigned int stage,
+static bool errata_probe_maee(unsigned int stage,
 			      unsigned long arch_id, unsigned long impid)
 {
-	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
+	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAEE))
 		return false;
 
 	if (arch_id != 0 || impid != 0)
@@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage,
 {
 	u32 cpu_req_errata = 0;
 
-	if (errata_probe_pbmt(stage, archid, impid))
-		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
+	if (errata_probe_maee(stage, archid, impid))
+		cpu_req_errata |= BIT(ERRATA_THEAD_MAEE);
 
 	errata_probe_cmo(stage, archid, impid);
 
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index ea33288f8a25..7c377e137b41 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -23,7 +23,7 @@
 #endif
 
 #ifdef CONFIG_ERRATA_THEAD
-#define	ERRATA_THEAD_PBMT 0
+#define	ERRATA_THEAD_MAEE 0
 #define	ERRATA_THEAD_PMU 1
 #define	ERRATA_THEAD_NUMBER 2
 #endif
@@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
  * in the default case.
  */
 #define ALT_SVPBMT_SHIFT 61
-#define ALT_THEAD_PBMT_SHIFT 59
+#define ALT_THEAD_MAEE_SHIFT 59
 #define ALT_SVPBMT(_val, prot)						\
 asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
 		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
 			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
 		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
-			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
+			ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE)	\
 		: "=r"(_val)						\
 		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
-		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
+		  "I"(prot##_THEAD >> ALT_THEAD_MAEE_SHIFT),		\
 		  "I"(ALT_SVPBMT_SHIFT),				\
-		  "I"(ALT_THEAD_PBMT_SHIFT))
+		  "I"(ALT_THEAD_MAEE_SHIFT))
 
-#ifdef CONFIG_ERRATA_THEAD_PBMT
+#ifdef CONFIG_ERRATA_THEAD_MAEE
 /*
  * IO/NOCACHE memory types are handled together with svpbmt,
  * so on T-Head chips, check if no other memory type is set,
@@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE(						\
 	"slli    t3, t3, %3\n\t"					\
 	"or      %0, %0, t3\n\t"					\
 	"2:",  THEAD_VENDOR_ID,						\
-		ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
+		ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE)		\
 	: "+r"(_val)							\
-	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
-	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),			\
-	  "I"(ALT_THEAD_PBMT_SHIFT)					\
+	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAEE_SHIFT),		\
+	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAEE_SHIFT),			\
+	  "I"(ALT_THEAD_MAEE_SHIFT)					\
 	: "t3")
 #else
 #define ALT_THEAD_PMA(_val)
-- 
2.44.0

[PATCH v2 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata

[Christoph Müllner]

T-Head's MAEE mechanism (non-compatible equivalent of RVI's Svpbmt)
is currently assumed for all T-Head harts. However, QEMU recently
decided to drop acceptance of guests that write reserved bits in PTEs.
As MAEE uses reserved bits in PTEs and Linux applies the MAEE errata
for all T-Head harts, this broke the Linux startup on QEMU emulations
of the C906 emulation.

This patch attempts to address this issue by testing the MAEE bit
in the th.sxstatus CSR. This CSR is available in HW and can be
emulated in QEMU.

This patch also makes the MAEE probing mechanism reliable, because
a test for the right combination of mvendorid, marchid, and mimpid
is not sufficient to enable MAEE.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 arch/riscv/errata/thead/errata.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 8c8a8a4b0421..dfa007039208 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -19,6 +19,9 @@
 #include <asm/patch.h>
 #include <asm/vendorid_list.h>
 
+#define CSR_TH_SXSTATUS		0x5c0
+#define SXSTATUS_MAEE		_AC(0x200000, UL)
+
 static bool errata_probe_maee(unsigned int stage,
 			      unsigned long arch_id, unsigned long impid)
 {
@@ -28,11 +31,14 @@ static bool errata_probe_maee(unsigned int stage,
 	if (arch_id != 0 || impid != 0)
 		return false;
 
-	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT ||
-	    stage == RISCV_ALTERNATIVES_MODULE)
-		return true;
+	if (stage != RISCV_ALTERNATIVES_EARLY_BOOT &&
+	    stage != RISCV_ALTERNATIVES_MODULE)
+		return false;
 
-	return false;
+	if (!(csr_read(CSR_TH_SXSTATUS) & SXSTATUS_MAEE))
+		return false;
+
+	return true;
 }
 
 /*
-- 
2.44.0

Re: [PATCH v2 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata

[Conor Dooley]

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On Fri, Mar 29, 2024 at 01:14:14PM +0100, Christoph Müllner wrote:
> T-Head's MAEE mechanism (non-compatible equivalent of RVI's Svpbmt)
> is currently assumed for all T-Head harts. However, QEMU recently
> decided to drop acceptance of guests that write reserved bits in PTEs.
> As MAEE uses reserved bits in PTEs and Linux applies the MAEE errata
> for all T-Head harts, this broke the Linux startup on QEMU emulations
> of the C906 emulation.
> 
> This patch attempts to address this issue by testing the MAEE bit
> in the th.sxstatus CSR. This CSR is available in HW and can be
> emulated in QEMU.
> 
> This patch also makes the MAEE probing mechanism reliable, because
> a test for the right combination of mvendorid, marchid, and mimpid
> is not sufficient to enable MAEE.
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Seems ideal to me, I'm guessing the QEMU guys were okay with emulating
the CSR. I don't see any screaming at the very least on the patch for
it.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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Re: [PATCH v2 1/2] riscv: thead: Rename T-Head PBMT to MAEE

[Conor Dooley]

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On Fri, Mar 29, 2024 at 01:14:13PM +0100, Christoph Müllner wrote:
> T-Head's vendor extension to set page attributes has the name
> MAEE (MMU address attribute extension).
> Let's rename it, so it is clear what this referes to.
> 
> See also:
>   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc

If there's a resend, make this a Link: tag please.

> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  arch/riscv/Kconfig.errata            |  8 ++++----
>  arch/riscv/errata/thead/errata.c     |  8 ++++----
>  arch/riscv/include/asm/errata_list.h | 20 ++++++++++----------
>  3 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 910ba8837add..2c24bef7e112 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -82,14 +82,14 @@ config ERRATA_THEAD
>  
>  	  Otherwise, please say "N" here to avoid unnecessary overhead.
>  
> -config ERRATA_THEAD_PBMT
> -	bool "Apply T-Head memory type errata"
> +config ERRATA_THEAD_MAEE
> +	bool "Apply T-Head's MMU address attribute (MAEE)"
>  	depends on ERRATA_THEAD && 64BIT && MMU
>  	select RISCV_ALTERNATIVE_EARLY
>  	default y

Since this defaults to enabled, changing the name should be fair game.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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Re: [PATCH v2 1/2] riscv: thead: Rename T-Head PBMT to MAEE

[Samuel Holland]

Hi Christoph,

On 2024-03-29 7:14 AM, Christoph Müllner wrote:
> T-Head's vendor extension to set page attributes has the name
> MAEE (MMU address attribute extension).
> Let's rename it, so it is clear what this referes to.
> 
> See also:
>   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc

My understanding is that MAEE is the name of the CSR bit and stands for "MMU (or
Memory) Attribute Extension Enable", so the name for the extension itself would
be "MAE" (just one E). This is similar to THEADISAEE => T-HEAD ISA Extension
Enable. Does that sound right?

Regards,
Samuel

> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  arch/riscv/Kconfig.errata            |  8 ++++----
>  arch/riscv/errata/thead/errata.c     |  8 ++++----
>  arch/riscv/include/asm/errata_list.h | 20 ++++++++++----------
>  3 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 910ba8837add..2c24bef7e112 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -82,14 +82,14 @@ config ERRATA_THEAD
>  
>  	  Otherwise, please say "N" here to avoid unnecessary overhead.
>  
> -config ERRATA_THEAD_PBMT
> -	bool "Apply T-Head memory type errata"
> +config ERRATA_THEAD_MAEE
> +	bool "Apply T-Head's MMU address attribute (MAEE)"
>  	depends on ERRATA_THEAD && 64BIT && MMU
>  	select RISCV_ALTERNATIVE_EARLY
>  	default y
>  	help
> -	  This will apply the memory type errata to handle the non-standard
> -	  memory type bits in page-table-entries on T-Head SoCs.
> +	  This will apply the memory type errata to handle T-Head's MMU address
> +	  attribute extension (MAEE).
>  
>  	  If you don't know what to do here, say "Y".
>  
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index b1c410bbc1ae..8c8a8a4b0421 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -19,10 +19,10 @@
>  #include <asm/patch.h>
>  #include <asm/vendorid_list.h>
>  
> -static bool errata_probe_pbmt(unsigned int stage,
> +static bool errata_probe_maee(unsigned int stage,
>  			      unsigned long arch_id, unsigned long impid)
>  {
> -	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAEE))
>  		return false;
>  
>  	if (arch_id != 0 || impid != 0)
> @@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage,
>  {
>  	u32 cpu_req_errata = 0;
>  
> -	if (errata_probe_pbmt(stage, archid, impid))
> -		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
> +	if (errata_probe_maee(stage, archid, impid))
> +		cpu_req_errata |= BIT(ERRATA_THEAD_MAEE);
>  
>  	errata_probe_cmo(stage, archid, impid);
>  
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index ea33288f8a25..7c377e137b41 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -23,7 +23,7 @@
>  #endif
>  
>  #ifdef CONFIG_ERRATA_THEAD
> -#define	ERRATA_THEAD_PBMT 0
> +#define	ERRATA_THEAD_MAEE 0
>  #define	ERRATA_THEAD_PMU 1
>  #define	ERRATA_THEAD_NUMBER 2
>  #endif
> @@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
>   * in the default case.
>   */
>  #define ALT_SVPBMT_SHIFT 61
> -#define ALT_THEAD_PBMT_SHIFT 59
> +#define ALT_THEAD_MAEE_SHIFT 59
>  #define ALT_SVPBMT(_val, prot)						\
>  asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
>  		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
>  			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
>  		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
> -			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
> +			ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE)	\
>  		: "=r"(_val)						\
>  		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
> -		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
> +		  "I"(prot##_THEAD >> ALT_THEAD_MAEE_SHIFT),		\
>  		  "I"(ALT_SVPBMT_SHIFT),				\
> -		  "I"(ALT_THEAD_PBMT_SHIFT))
> +		  "I"(ALT_THEAD_MAEE_SHIFT))
>  
> -#ifdef CONFIG_ERRATA_THEAD_PBMT
> +#ifdef CONFIG_ERRATA_THEAD_MAEE
>  /*
>   * IO/NOCACHE memory types are handled together with svpbmt,
>   * so on T-Head chips, check if no other memory type is set,
> @@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE(						\
>  	"slli    t3, t3, %3\n\t"					\
>  	"or      %0, %0, t3\n\t"					\
>  	"2:",  THEAD_VENDOR_ID,						\
> -		ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
> +		ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE)		\
>  	: "+r"(_val)							\
> -	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
> -	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),			\
> -	  "I"(ALT_THEAD_PBMT_SHIFT)					\
> +	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAEE_SHIFT),		\
> +	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAEE_SHIFT),			\
> +	  "I"(ALT_THEAD_MAEE_SHIFT)					\
>  	: "t3")
>  #else
>  #define ALT_THEAD_PMA(_val)

Re: [PATCH v2 1/2] riscv: thead: Rename T-Head PBMT to MAEE

[Christoph Müllner]

On Thu, Apr 4, 2024 at 8:15 PM Samuel Holland <samuel.holland@sifive.com> wrote:
>
> Hi Christoph,
>
> On 2024-03-29 7:14 AM, Christoph Müllner wrote:
> > T-Head's vendor extension to set page attributes has the name
> > MAEE (MMU address attribute extension).
> > Let's rename it, so it is clear what this referes to.
> >
> > See also:
> >   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc
>
> My understanding is that MAEE is the name of the CSR bit and stands for "MMU (or
> Memory) Attribute Extension Enable", so the name for the extension itself would
> be "MAE" (just one E). This is similar to THEADISAEE => T-HEAD ISA Extension
> Enable. Does that sound right?

Yes, you are right.
I noticed that before as well but did not care too much about it.
Now that I'm not the only one who sees it, I've created a PR for the spec
to rename the extension to XTheadMae:
  https://github.com/T-head-Semi/thead-extension-spec/pull/48
The PR has already been merged, so I'll provide a revised patch.

Thanks!

>
> Regards,
> Samuel
>
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >  arch/riscv/Kconfig.errata            |  8 ++++----
> >  arch/riscv/errata/thead/errata.c     |  8 ++++----
> >  arch/riscv/include/asm/errata_list.h | 20 ++++++++++----------
> >  3 files changed, 18 insertions(+), 18 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index 910ba8837add..2c24bef7e112 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -82,14 +82,14 @@ config ERRATA_THEAD
> >
> >         Otherwise, please say "N" here to avoid unnecessary overhead.
> >
> > -config ERRATA_THEAD_PBMT
> > -     bool "Apply T-Head memory type errata"
> > +config ERRATA_THEAD_MAEE
> > +     bool "Apply T-Head's MMU address attribute (MAEE)"
> >       depends on ERRATA_THEAD && 64BIT && MMU
> >       select RISCV_ALTERNATIVE_EARLY
> >       default y
> >       help
> > -       This will apply the memory type errata to handle the non-standard
> > -       memory type bits in page-table-entries on T-Head SoCs.
> > +       This will apply the memory type errata to handle T-Head's MMU address
> > +       attribute extension (MAEE).
> >
> >         If you don't know what to do here, say "Y".
> >
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index b1c410bbc1ae..8c8a8a4b0421 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -19,10 +19,10 @@
> >  #include <asm/patch.h>
> >  #include <asm/vendorid_list.h>
> >
> > -static bool errata_probe_pbmt(unsigned int stage,
> > +static bool errata_probe_maee(unsigned int stage,
> >                             unsigned long arch_id, unsigned long impid)
> >  {
> > -     if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> > +     if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAEE))
> >               return false;
> >
> >       if (arch_id != 0 || impid != 0)
> > @@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage,
> >  {
> >       u32 cpu_req_errata = 0;
> >
> > -     if (errata_probe_pbmt(stage, archid, impid))
> > -             cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
> > +     if (errata_probe_maee(stage, archid, impid))
> > +             cpu_req_errata |= BIT(ERRATA_THEAD_MAEE);
> >
> >       errata_probe_cmo(stage, archid, impid);
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index ea33288f8a25..7c377e137b41 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -23,7 +23,7 @@
> >  #endif
> >
> >  #ifdef CONFIG_ERRATA_THEAD
> > -#define      ERRATA_THEAD_PBMT 0
> > +#define      ERRATA_THEAD_MAEE 0
> >  #define      ERRATA_THEAD_PMU 1
> >  #define      ERRATA_THEAD_NUMBER 2
> >  #endif
> > @@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,  \
> >   * in the default case.
> >   */
> >  #define ALT_SVPBMT_SHIFT 61
> > -#define ALT_THEAD_PBMT_SHIFT 59
> > +#define ALT_THEAD_MAEE_SHIFT 59
> >  #define ALT_SVPBMT(_val, prot)                                               \
> >  asm(ALTERNATIVE_2("li %0, 0\t\nnop",                                 \
> >                 "li %0, %1\t\nslli %0,%0,%3", 0,                      \
> >                       RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,  \
> >                 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,        \
> > -                     ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)    \
> > +                     ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE)    \
> >               : "=r"(_val)                                            \
> >               : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),               \
> > -               "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),            \
> > +               "I"(prot##_THEAD >> ALT_THEAD_MAEE_SHIFT),            \
> >                 "I"(ALT_SVPBMT_SHIFT),                                \
> > -               "I"(ALT_THEAD_PBMT_SHIFT))
> > +               "I"(ALT_THEAD_MAEE_SHIFT))
> >
> > -#ifdef CONFIG_ERRATA_THEAD_PBMT
> > +#ifdef CONFIG_ERRATA_THEAD_MAEE
> >  /*
> >   * IO/NOCACHE memory types are handled together with svpbmt,
> >   * so on T-Head chips, check if no other memory type is set,
> > @@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE(                                         \
> >       "slli    t3, t3, %3\n\t"                                        \
> >       "or      %0, %0, t3\n\t"                                        \
> >       "2:",  THEAD_VENDOR_ID,                                         \
> > -             ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)            \
> > +             ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE)            \
> >       : "+r"(_val)                                                    \
> > -     : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),              \
> > -       "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),                 \
> > -       "I"(ALT_THEAD_PBMT_SHIFT)                                     \
> > +     : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAEE_SHIFT),              \
> > +       "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAEE_SHIFT),                 \
> > +       "I"(ALT_THEAD_MAEE_SHIFT)                                     \
> >       : "t3")
> >  #else
> >  #define ALT_THEAD_PMA(_val)
>