[PATCH 00/12] Support Lunar Lake and Arrow Lake core PMU

kan.liang
2024-04-04T14:07:37Z

From the core PMU' perspective, the Lunar Lake and Arrow Lake are the
same, which are similar to the previous generation Meteor Lake. Both are
hybrid platforms, with e-core and p-core.

The key differences include:
- The e-core supports 3 new fixed counters
- The p-core supports an updated PEBS Data Source format
- More GP counters (Updated event constraint table)
- New Architectural performance monitoring V6
(New Perfmon MSRs aliasing, umask2, eq).
- New PEBS format V6 (Counters Snapshotting group)
- New RDPMC metrics clear mode

The details for the above new features can be found in the Intel
Architecture Instruction Set Extensions and Future Features (052).
https://cdrdv2.intel.com/v1/dl/getContent/671368

The counters may not be continuous anymore. Patch 1-2 converts the max
number of counters to a mask of counters. The change is a generic change
which impacts all X86 platforms.

Patch 3-4 supports all the legacy features on LNL and ARL.

Patch 5-7 supports the new Architectural performance monitoring V6.

Patch 8-11 supports the new PEBS format V6.

Patch 12 supports the new RDPMC metrics clear mode.

Kan Liang (12):
perf/x86/intel: Support the PEBS event mask
perf/x86: Support counter mask
perf/x86: Add Lunar Lake and Arrow Lake support
perf/x86/intel: Support new data source for Lunar Lake
perf/x86: Add config_mask to represent EVENTSEL bitmask
perf/x86/intel: Support PERFEVTSEL extension
perf/x86/intel: Support Perfmon MSRs aliasing
perf/x86: Extend event update interface
perf: Extend perf_output_read
perf/x86/intel: Move PEBS event update after the sample output
perf/x86/intel: Support PEBS counters snapshotting
perf/x86/intel: Support RDPMC metrics clear mode

arch/x86/events/amd/core.c | 26 +-
arch/x86/events/core.c | 123 +++----
arch/x86/events/intel/core.c | 466 ++++++++++++++++++++-------
arch/x86/events/intel/ds.c | 267 +++++++++++++--
arch/x86/events/intel/knc.c | 2 +-
arch/x86/events/intel/p4.c | 12 +-
arch/x86/events/intel/p6.c | 2 +-
arch/x86/events/perf_event.h | 81 ++++-
arch/x86/events/perf_event_flags.h | 2 +-
arch/x86/events/zhaoxin/core.c | 14 +-
arch/x86/include/asm/intel_ds.h | 6 +
arch/x86/include/asm/msr-index.h | 6 +
arch/x86/include/asm/perf_event.h | 27 ++
include/uapi/linux/perf_event.h | 6 +-
kernel/events/core.c | 15 +-
tools/perf/Documentation/topdown.txt | 9 +-
16 files changed, 810 insertions(+), 254 deletions(-)

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2.35.1