From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/3] clocksource/drivers/timer-clint: Add T-Head C9xx clint
Date: Sat, 6 Apr 2024 19:21:59 +0800 [thread overview]
Message-ID: <20240406112159.1634-4-jszhang@kernel.org> (raw)
In-Reply-To: <20240406112159.1634-1-jszhang@kernel.org>
The mtimecmp in T-Head C9xx clint only supports 32bit read/write,
implement such support.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/clocksource/timer-clint.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 0d3890e00b75..655ea81071ff 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -39,6 +39,7 @@ static u64 __iomem *clint_timer_cmp;
static u64 __iomem *clint_timer_val;
static unsigned long clint_timer_freq;
static unsigned int clint_timer_irq;
+static bool is_c900_clint;
#ifdef CONFIG_RISCV_M_MODE
u64 __iomem *clint_time_val;
@@ -135,6 +136,19 @@ static int clint_clock_shutdown(struct clock_event_device *evt)
return 0;
}
+static int c900_clint_clock_next_event(unsigned long delta,
+ struct clock_event_device *ce)
+{
+ void __iomem *r = clint_timer_cmp +
+ cpuid_to_hartid_map(smp_processor_id());
+ u64 val = clint_get_cycles64() + delta;
+
+ csr_set(CSR_IE, IE_TIE);
+ writel_relaxed(val, r);
+ writel_relaxed(val >> 32, r + 4);
+ return 0;
+}
+
static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
.name = "clint_clockevent",
.features = CLOCK_EVT_FEAT_ONESHOT,
@@ -148,6 +162,9 @@ static int clint_timer_starting_cpu(unsigned int cpu)
{
struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
+ if (is_c900_clint)
+ ce->set_next_event = c900_clint_clock_next_event;
+
ce->cpumask = cpumask_of(cpu);
clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX);
@@ -291,5 +308,12 @@ static int __init clint_timer_init_dt(struct device_node *np)
return rc;
}
+static int __init c900_clint_timer_init_dt(struct device_node *np)
+{
+ is_c900_clint = true;
+ return clint_timer_init_dt(np);
+}
+
TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer2, "thead,c900-clint", c900_clint_timer_init_dt);
--
2.43.0
prev parent reply other threads:[~2024-04-06 11:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-06 11:21 [PATCH v2 0/3] riscv: improve nommu and timer-clint Jisheng Zhang
2024-04-06 11:21 ` [PATCH v2 1/3] riscv: nommu: remove PAGE_OFFSET hardcoding Jisheng Zhang
2024-04-06 11:21 ` [PATCH v2 2/3] clocksource/drivers/timer-clint: Add option to use CSR instead of mtime Jisheng Zhang
2024-04-09 14:26 ` Conor Dooley
2024-04-09 14:48 ` Jisheng Zhang
2024-04-10 10:30 ` Jisheng Zhang
2024-04-24 11:01 ` Conor Dooley
2024-04-06 11:21 ` Jisheng Zhang [this message]
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