[PATCH v10 12/13] clk: hisilicon: hix5hd2: Convert into platform driver module

David Yang
2024-04-16T10:05:38Z

drivers/clk/hisilicon/clk-hix5hd2.c | 86 ++++++++++++++++++-----------
1 file changed, 53 insertions(+), 33 deletions(-)

diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
index 64bdd3f05725..e46a516cd0eb 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -4,13 +4,18 @@
* Copyright (c) 2014 Hisilicon Limited.
*/

-#include <linux/of_address.h>
#include <dt-bindings/clock/hix5hd2-clock.h>
+
#include <linux/slab.h>
#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
#include "clk.h"

-static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
+static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] = {
{ HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, },
{ HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, },
{ HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, },
@@ -43,19 +48,19 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
{ HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, },
};

-static const char *const sfc_mux_p[] __initconst = {
+static const char *const sfc_mux_p[] = {
"24m", "150m", "200m", "100m", "75m", };
static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};

-static const char *const sdio_mux_p[] __initconst = {
+static const char *const sdio_mux_p[] = {
"75m", "100m", "50m", "15m", };
static u32 sdio_mux_table[] = {0, 1, 2, 3};

-static const char *const fephy_mux_p[] __initconst = { "25m", "125m"};
+static const char *const fephy_mux_p[] = { "25m", "125m"};
static u32 fephy_mux_table[] = {0, 1};

-static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
+static struct hisi_mux_clock hix5hd2_mux_clks[] = {
{ HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
{ HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
@@ -67,7 +72,7 @@ static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
};

-static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
+static struct hisi_gate_clock hix5hd2_gate_clks[] = {
/* sfc */
{ HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
@@ -153,7 +158,7 @@ struct hix5hd2_clk_complex {
u32 phy_rst_mask;
};

-static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = {
+static struct hix5hd2_complex_clock hix5hd2_complex_clks[] = {
{"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK,
0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
{"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK,
@@ -249,21 +254,22 @@ static const struct clk_ops clk_complex_ops = {
.disable = clk_complex_disable,
};

-static void __init
-hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
+static int
+hix5hd2_clk_register_complex(struct device *dev, const void *clocks, size_t num,
struct hisi_clock_data *data)
{
+ const struct hix5hd2_complex_clock *clks = clocks;
void __iomem *base = data->base;
int i;

- for (i = 0; i < nums; i++) {
+ for (i = 0; i < num; i++) {
struct hix5hd2_clk_complex *p_clk;
struct clk *clk;
struct clk_init_data init;

p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
if (!p_clk)
- return;
+ return -ENOMEM;

init.name = clks[i].name;
if (clks[i].type == TYPE_ETHER)
@@ -289,31 +295,45 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
kfree(p_clk);
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
- continue;
+ return PTR_ERR(p_clk);
}

data->clk_data.clks[clks[i].id] = clk;
}
-}

-static void __init hix5hd2_clk_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
- if (!clk_data)
- return;
-
- hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
- ARRAY_SIZE(hix5hd2_fixed_rate_clks),
- clk_data);
- hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
- clk_data);
- hisi_clk_register_gate(hix5hd2_gate_clks,
- ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
- hix5hd2_clk_register_complex(hix5hd2_complex_clks,
- ARRAY_SIZE(hix5hd2_complex_clks),
- clk_data);
+ return 0;
}

-CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
+static const struct hisi_clocks hix5hd2_clks = {
+ .nr = HIX5HD2_NR_CLKS,
+ .fixed_rate_clks = hix5hd2_fixed_rate_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hix5hd2_fixed_rate_clks),
+ .mux_clks = hix5hd2_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hix5hd2_mux_clks),
+ .gate_clks = hix5hd2_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hix5hd2_gate_clks),
+ .customized_clks = hix5hd2_complex_clks,
+ .customized_clks_num = ARRAY_SIZE(hix5hd2_complex_clks),
+ .clk_register_customized = hix5hd2_clk_register_complex,
+};
+
+static const struct of_device_id hix5hd2_clk_match_table[] = {
+ { .compatible = "hisilicon,hix5hd2-clock",
+ .data = &hix5hd2_clks },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hix5hd2_clk_match_table);
+
+static struct platform_driver hix5hd2_clk_driver = {
+ .probe = hisi_clk_probe,
+ .remove_new = hisi_clk_remove,
+ .driver = {
+ .name = "hix5hd2-clock",
+ .of_match_table = hix5hd2_clk_match_table,
+ },
+};
+
+module_platform_driver(hix5hd2_clk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hix5hd2 Clock Driver");
--
2.43.0