From: Sean Anderson <sean.anderson@linux.dev>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
Michal Simek <michal.simek@amd.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Sean Anderson <sean.anderson@linux.dev>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org
Subject: [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys
Date: Mon, 22 Apr 2024 15:58:58 -0400 [thread overview]
Message-ID: <20240422195904.3591683-2-sean.anderson@linux.dev> (raw)
In-Reply-To: <20240422195904.3591683-1-sean.anderson@linux.dev>
Add phys properties so Linux can power-on/configure the GTR
transcievers.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 426f90a47f35..02315669b831 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -61,6 +61,14 @@ properties:
interrupt-map:
maxItems: 4
+ phys:
+ maxItems: 4
+
+ phy-names:
+ maxItems: 4
+ items:
+ - pattern: '^pcie-phy[0-3]$'
+
power-domains:
maxItems: 1
--
2.35.1.1320.gc452695387.dirty
next prev parent reply other threads:[~2024-04-22 19:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 19:58 [PATCH 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-04-22 19:58 ` Sean Anderson [this message]
2024-04-22 21:28 ` [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys Rob Herring
2024-04-22 21:30 ` Sean Anderson
2024-04-23 12:38 ` Rob Herring
2024-04-23 12:44 ` Rob Herring
2024-04-23 15:18 ` Sean Anderson
2024-04-23 18:43 ` kernel test robot
2024-04-22 19:58 ` [PATCH 2/7] PCI: xilinx-nwl: Fix off-by-one Sean Anderson
2024-04-22 19:59 ` [PATCH 3/7] PCI: xilinx-nwl: Fix register misspelling Sean Anderson
2024-04-22 19:59 ` [PATCH 4/7] PCI: xilinx-nwl: Rate-limit misc interrupt messages Sean Anderson
2024-04-22 19:59 ` [PATCH 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal Sean Anderson
2024-04-22 19:59 ` [PATCH 6/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-04-22 19:59 ` [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys Sean Anderson
2024-04-23 6:15 ` Michal Simek
2024-04-24 9:11 ` Havalige, Thippeswamy
2024-04-24 11:27 ` Michal Simek
2024-04-24 12:37 ` Havalige, Thippeswamy
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