From: Rob Herring <robh@kernel.org>
To: Sean Anderson <sean.anderson@linux.dev>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>,
"Michal Simek" <michal.simek@amd.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys
Date: Tue, 23 Apr 2024 07:44:56 -0500 [thread overview]
Message-ID: <20240423124456.GB4105016-robh@kernel.org> (raw)
In-Reply-To: <20240422195904.3591683-2-sean.anderson@linux.dev>
On Mon, Apr 22, 2024 at 03:58:58PM -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
>
> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
> ---
>
> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 426f90a47f35..02315669b831 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -61,6 +61,14 @@ properties:
> interrupt-map:
> maxItems: 4
>
> + phys:
> + maxItems: 4
> +
> + phy-names:
> + maxItems: 4
> + items:
> + - pattern: '^pcie-phy[0-3]$'
The names here are pointless and redundant. Names are local to the
device, so 'pcie' is redundant. They only refer to PHYs, so 'phy' is
redundant too. All you are left with is the index of the entry.
Now if PCIe can work on only lanes 2 and 3 or similar, then maybe
-names becomes useful.
Rob
next prev parent reply other threads:[~2024-04-23 12:44 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 19:58 [PATCH 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-04-22 19:58 ` [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys Sean Anderson
2024-04-22 21:28 ` Rob Herring
2024-04-22 21:30 ` Sean Anderson
2024-04-23 12:38 ` Rob Herring
2024-04-23 12:44 ` Rob Herring [this message]
2024-04-23 15:18 ` Sean Anderson
2024-04-23 18:43 ` kernel test robot
2024-04-22 19:58 ` [PATCH 2/7] PCI: xilinx-nwl: Fix off-by-one Sean Anderson
2024-04-22 19:59 ` [PATCH 3/7] PCI: xilinx-nwl: Fix register misspelling Sean Anderson
2024-04-22 19:59 ` [PATCH 4/7] PCI: xilinx-nwl: Rate-limit misc interrupt messages Sean Anderson
2024-04-22 19:59 ` [PATCH 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal Sean Anderson
2024-04-22 19:59 ` [PATCH 6/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-04-22 19:59 ` [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys Sean Anderson
2024-04-23 6:15 ` Michal Simek
2024-04-24 9:11 ` Havalige, Thippeswamy
2024-04-24 11:27 ` Michal Simek
2024-04-24 12:37 ` Havalige, Thippeswamy
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