[tip: x86/irq] x86/irq: Extend checks for pending vectors to posted interrupts

tip-bot2 for Jacob Pan
2024-04-30T13:28:42Z

The following commit has been merged into the x86/irq branch of tip:

Commit-ID: ce0a92871179f8ca58ae8e3cf50e726a163bf831
Gitweb: https://git.kernel.org/tip/ce0a92871179f8ca58ae8e3cf50e726a163bf831
Author: Jacob Pan <jacob.jun.pan@linux.intel.com>
AuthorDate: Tue, 23 Apr 2024 10:41:12 -07:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 30 Apr 2024 00:54:43 +02:00

x86/irq: Extend checks for pending vectors to posted interrupts

During interrupt affinity change, it is possible to have interrupts delivered
to the old CPU after the affinity has changed to the new one. To prevent lost
interrupts, local APIC IRR is checked on the old CPU. Similar checks must be
done for posted MSIs given the same reason.

Consider the following scenario:
Device system agent iommu memory CPU/LAPIC
1 FEEX_XXXX
2 Interrupt request
3 Fetch IRTE ->
4 ->Atomic Swap PID.PIR(vec)
Push to Global Observable(GO)
5 if (ON*)
done;*
else
6 send a notification ->

* ON: outstanding notification, 1 will suppress new notifications

If the affinity change happens between 3 and 5 in the IOMMU, the old CPU's
posted interrupt request (PIR) could have the pending bit set for the
vector being moved.

Add a helper function to check individual vector status. Then use the
helper to check for pending interrupts on the source CPU's PID.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240423174114.526704-11-jacob.jun.pan@linux.intel.com
---
arch/x86/include/asm/apic.h | 3 ++-
arch/x86/include/asm/posted_intr.h | 18 ++++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 50f9781..5644c39 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -14,6 +14,7 @@
#include <asm/msr.h>
#include <asm/hardirq.h>
#include <asm/io.h>
+#include <asm/posted_intr.h>

#define ARCH_APICTIMER_STOPS_ON_C3 1

@@ -508,7 +509,7 @@ static inline bool is_vector_pending(unsigned int vector)
if (irr & (1 << (vector % 32)))
return true;

- return false;
+ return pi_pending_this_cpu(vector);
}

/*
diff --git a/arch/x86/include/asm/posted_intr.h b/arch/x86/include/asm/posted_intr.h
index 6f84f67..de788b4 100644
--- a/arch/x86/include/asm/posted_intr.h
+++ b/arch/x86/include/asm/posted_intr.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _X86_POSTED_INTR_H
#define _X86_POSTED_INTR_H
+#include <asm/irq_vectors.h>

#define POSTED_INTR_ON 0
#define POSTED_INTR_SN 1
@@ -92,8 +93,25 @@ static inline void __pi_clear_sn(struct pi_desc *pi_desc)
}

#ifdef CONFIG_X86_POSTED_MSI
+/*
+ * Not all external vectors are subject to interrupt remapping, e.g. IOMMU's
+ * own interrupts. Here we do not distinguish them since those vector bits in
+ * PIR will always be zero.
+ */
+static inline bool pi_pending_this_cpu(unsigned int vector)
+{
+ struct pi_desc *pid = this_cpu_ptr(&posted_msi_pi_desc);
+
+ if (WARN_ON_ONCE(vector > NR_VECTORS || vector < FIRST_EXTERNAL_VECTOR))
+ return false;
+
+ return test_bit(vector, (unsigned long *)pid->pir);
+}
+
extern void intel_posted_msi_init(void);
#else
+static inline bool pi_pending_this_cpu(unsigned int vector) { return false; }
+
static inline void intel_posted_msi_init(void) {};
#endif /* X86_POSTED_MSI */