From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D57D4137914; Tue, 7 May 2024 23:11:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715123491; cv=none; b=q61uFzUOZJ+7MQidoK3tC+YiUrIYA/6uvDxkvRYGWQaGW59iFdZ+BeCRqyVA1xRv7pLnKe7VwxnRtpYMkeU3pcYnfEgoeZce4Y8AEvEQnPMtFhbCKurq46QnC2ApkVh79x6i8F+lRWD7gFJajowP4SonWq6bAhhtfOW2E26AtII= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715123491; c=relaxed/simple; bh=utTm6v9FpIRRisvyk/NnR1Enbyu0MqYnRldgniZmi14=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Py+9Frk6f/ygLlXd2Lk00RXMMHveGkUDRRj49j2zd2OmsFybyM0Sg9U5elzk+vGlh74vygPgy4z9LiEJnWUlWetq00CYsVpxXlcQrY8UN8OrAfnu67O35Z11X2RbJdtOlk7+X3oysblKZAcMz1nfDC80uyInWi4iWPZGnEXPoJs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SPr8ZHTP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SPr8ZHTP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 837ECC3277B; Tue, 7 May 2024 23:11:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715123491; bh=utTm6v9FpIRRisvyk/NnR1Enbyu0MqYnRldgniZmi14=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SPr8ZHTPC10EbFc/RFupxRzv0jqNf9GOBgyGR9xCoi3nVL39hGAbZNowXBMVlw0sY JMZs9cSZVsu3SIqoT9prhZ/SzVI0dd8RR4Upb4mWFWU0yVRCInBpJpzsiZ9LYWNPtB v+2JbYbnyNNCTOEw17TVku7fOM+V5qxrVFYQGkdProKc++PjfB2vFu4kKJtYzQNqYu PHx24qRGB1+5Mm+T6UJ7kKnOW+BHY8+77MFetykTA/QIeCRCm1TIZF+v1OIt83eUG5 QANWSzSAWagjoND7I5OwsSqK/bRBXWh5jR05bRmViW8voG4SQ/vHVScoG4FbwvGaah FVmmmHuiR0teg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Swapnil Patel , Dmytro Laktyushkin , Aurabindo Pillai , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, chiahsuan.chung@amd.com, charlene.liu@amd.com, eric.bernstein@amd.com, nicholas.kazlauskas@amd.com, qingqing.zhuo@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.6 29/43] drm/amd/display: Add dtbclk access to dcn315 Date: Tue, 7 May 2024 19:09:50 -0400 Message-ID: <20240507231033.393285-29-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240507231033.393285-1-sashal@kernel.org> References: <20240507231033.393285-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.30 Content-Transfer-Encoding: 8bit From: Swapnil Patel [ Upstream commit a01b64f31d65bdc917d1afb4cec9915beb6931be ] [Why & How] Currently DCN315 clk manager is missing code to enable/disable dtbclk. Because of this, "optimized_required" flag is constantly set and this prevents FreeSync from engaging for certain high bandwidth display Modes which require DTBCLK. Reviewed-by: Dmytro Laktyushkin Acked-by: Aurabindo Pillai Signed-off-by: Swapnil Patel Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index 8776055bbeaae..d4d3f58a613f7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -145,6 +145,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, */ clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; if (safe_to_lower) { + if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { + dcn315_smu_set_dtbclk(clk_mgr, false); + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } /* check that we're not already in lower */ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { display_count = dcn315_get_active_display_cnt_wa(dc, context); @@ -160,6 +164,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, } } } else { + if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { + dcn315_smu_set_dtbclk(clk_mgr, true); + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } /* check that we're not already in D0 */ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { union display_idle_optimization_u idle_info = { 0 }; -- 2.43.0