From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Esther Shimanovich <eshimanovich@chromium.org>
Cc: Lukas Wunner <lukas@wunner.de>,
Mario Limonciello <mario.limonciello@amd.com>,
Dmitry Torokhov <dmitry.torokhov@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Rajat Jain <rajatja@google.com>
Subject: Re: [PATCH v4] PCI: Relabel JHL6540 on Lenovo X1 Carbon 7,8
Date: Sat, 11 May 2024 08:43:23 +0300 [thread overview]
Message-ID: <20240511054323.GE4162345@black.fi.intel.com> (raw)
In-Reply-To: <20240511043832.GD4162345@black.fi.intel.com>
On Sat, May 11, 2024 at 07:38:32AM +0300, Mika Westerberg wrote:
> They are not integrated Thunderbolt PCIe root ports.
For the clarity, Intel integrated Thunderbolt 3 controller first in Ice
Lake, then Thunderbolt 4 controller in Tiger Lake and forward (Alder
Lake, Raptor Lake, Meteor Lake). Anything else, including Comet Lake and
the like are using discrete controllers such as Alpine Ridge, Titan
Ridge (both Thunderbolt 3) and Maple Ridge (Thunderbolt 4), and Barlow
Ridge (Thunderbolt 5) where the controller is either soldered on the
motherboard or connected to a PCIe slot.
Sorry for not opening this up earlier.
There are some combinations where the integrated controller is disabled
and a discrete one is being used but again that should match the second
"rule".
next prev parent reply other threads:[~2024-05-11 5:43 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 20:53 [PATCH v4] PCI: Relabel JHL6540 on Lenovo X1 Carbon 7,8 Esther Shimanovich
2023-12-21 23:15 ` Dmitry Torokhov
2023-12-27 0:15 ` Bjorn Helgaas
2023-12-28 13:25 ` Lukas Wunner
2023-12-28 13:39 ` Mika Westerberg
2024-01-17 21:21 ` Esther Shimanovich
2024-01-18 6:00 ` Mika Westerberg
2024-01-18 15:47 ` Mario Limonciello
2024-01-18 16:12 ` Dmitry Torokhov
2024-01-18 16:21 ` Dmitry Torokhov
2024-01-19 5:37 ` Mika Westerberg
2024-01-19 7:48 ` Mika Westerberg
2024-01-19 10:22 ` Mika Westerberg
2024-01-19 16:03 ` Esther Shimanovich
2024-01-22 6:10 ` Mika Westerberg
2024-01-22 23:50 ` Mario Limonciello
2024-01-23 6:18 ` Mika Westerberg
2024-01-25 23:45 ` Esther Shimanovich
2024-04-15 22:34 ` Esther Shimanovich
2024-04-16 5:03 ` Mika Westerberg
2024-04-18 19:43 ` Esther Shimanovich
2024-04-19 4:49 ` Mika Westerberg
2024-04-22 19:17 ` Esther Shimanovich
2024-04-22 19:21 ` Mario Limonciello
2024-04-23 5:33 ` Mika Westerberg
2024-04-23 8:31 ` Lukas Wunner
2024-04-23 8:40 ` Mika Westerberg
2024-04-23 16:59 ` Mario Limonciello
2024-04-24 8:56 ` Mika Westerberg
2024-04-25 21:16 ` Esther Shimanovich
2024-04-26 4:52 ` Mika Westerberg
2024-04-26 15:58 ` Esther Shimanovich
2024-04-27 5:35 ` Lukas Wunner
2024-04-27 7:41 ` Mika Westerberg
2024-04-27 7:08 ` Lukas Wunner
2024-04-27 15:09 ` Lukas Wunner
2024-05-01 22:23 ` Esther Shimanovich
2024-05-02 4:38 ` Mika Westerberg
2024-05-02 9:54 ` Mario Limonciello
2024-05-02 10:07 ` Mika Westerberg
2024-05-08 5:14 ` Lukas Wunner
2024-05-10 5:26 ` Mika Westerberg
2024-05-10 15:44 ` Esther Shimanovich
2024-05-11 4:38 ` Mika Westerberg
2024-05-11 5:43 ` Mika Westerberg [this message]
2024-05-15 18:53 ` Esther Shimanovich
2024-05-15 20:35 ` Lukas Wunner
2024-05-15 20:51 ` Lukas Wunner
2024-05-15 21:44 ` Esther Shimanovich
2024-05-16 8:30 ` Mika Westerberg
2024-05-16 10:03 ` Mika Westerberg
2024-06-24 15:58 ` Esther Shimanovich
2024-06-26 8:05 ` Mika Westerberg
2024-07-26 18:17 ` Esther Shimanovich
2024-07-29 8:16 ` Mika Westerberg
2024-06-26 8:50 ` Lukas Wunner
2024-06-26 8:59 ` Mika Westerberg
2024-07-28 15:41 ` Lukas Wunner
2024-07-29 8:04 ` Mika Westerberg
2024-08-25 14:29 ` Lukas Wunner
2024-08-26 5:41 ` Mika Westerberg
2024-08-28 20:12 ` Esther Shimanovich
2024-05-16 9:16 ` Mika Westerberg
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