Re: [PATCH V2 2/9] PCI: Add TPH related register definition

Wei Huang
2024-06-10T20:00:30Z

On 6/7/24 11:17, Jonathan Cameron wrote:
> On Fri, 31 May 2024 16:38:34 -0500
> Wei Huang <wei.huang2@amd.com> wrote:
>> /* TPH Requester */
>> #define PCI_TPH_CAP 4 /* capability register */
>> +#define PCI_TPH_CAP_NO_ST 0x1 /* no ST mode supported */
>> +#define PCI_TPH_CAP_NO_ST_SHIFT 0x0 /* no ST mode supported shift */
>> +#define PCI_TPH_CAP_INT_VEC 0x2 /* interrupt vector mode supported */
>> +#define PCI_TPH_CAP_INT_VEC_SHIFT 0x1 /* interrupt vector mode supported shift */
>> +#define PCI_TPH_CAP_DS 0x4 /* device specific mode supported */
>> +#define PCI_TPH_CAP_DS_SHIFT 0x4 /* device specific mode supported shift */
>> #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
>> -#define PCI_TPH_LOC_NONE 0x000 /* no location */
>> -#define PCI_TPH_LOC_CAP 0x200 /* in capability */
>> -#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
>
> It's a userspace header, relatively unlikely to be safe to change it...
> This would also be inconsistent with how some other registers are defined in here.
>
> I'd love it if we could tidy this up, but we are stuck by this being
> in uapi.

Alex Williamson had a similar comment in another email. In V3, I will
only add (necessary) new definitions and refrain from touching the
existing ones.