Re: [PATCH v3 15/21] iommu/vt-d: Add helper to allocate paging domain

Baolu Lu
2024-06-20T01:16:57Z

On 6/19/24 11:12 PM, Jason Gunthorpe wrote:
> On Mon, Jun 10, 2024 at 04:55:49PM +0800, Lu Baolu wrote:
>> The domain_alloc_user operation is currently implemented by allocating a
>> paging domain using iommu_domain_alloc(). This is because it needs to fully
>> initialize the domain before return. Add a helper to do this to avoid using
>> iommu_domain_alloc().
>>
>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
>> ---
>> drivers/iommu/intel/iommu.c | 87 +++++++++++++++++++++++++++++++++----
>> 1 file changed, 78 insertions(+), 9 deletions(-)
> It seems Ok, but I have some small thoughts
>
> Reviewed-by: Jason Gunthorpe<jgg@nvidia.com>
>
>> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
>> index 2e9811bf2a4e..ccde5f5972e4 100644
>> --- a/drivers/iommu/intel/iommu.c
>> +++ b/drivers/iommu/intel/iommu.c
>> @@ -3633,6 +3633,79 @@ static struct iommu_domain blocking_domain = {
>> }
>> };
>>
>> +static int iommu_superpage_capability(struct intel_iommu *iommu, bool first_stage)
>> +{
>> + if (!intel_iommu_superpage)
>> + return 0;
>> +
>> + if (first_stage)
>> + return cap_fl1gp_support(iommu->cap) ? 2 : 1;
>> +
>> + return fls(cap_super_page_val(iommu->cap));
>> +}
>> +
>> +static struct dmar_domain *paging_domain_alloc(struct device *dev, bool first_stage)
>> +{
>> + struct device_domain_info *info = dev_iommu_priv_get(dev);
>> + struct intel_iommu *iommu = info->iommu;
>> + struct dmar_domain *domain;
>> + int addr_width;
>> +
>> + domain = kzalloc(sizeof(*domain), GFP_KERNEL);
>> + if (!domain)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + INIT_LIST_HEAD(&domain->devices);
>> + INIT_LIST_HEAD(&domain->dev_pasids);
>> + INIT_LIST_HEAD(&domain->cache_tags);
>> + spin_lock_init(&domain->lock);
>> + spin_lock_init(&domain->cache_lock);
>> + xa_init(&domain->iommu_array);
> You should probably split more, with an 'alloc struct dmar_domain'
> function that can be used by SVA and others too.
>
>> + domain->nid = dev_to_node(dev);
>> + domain->has_iotlb_device = info->ats_enabled;
>> + domain->use_first_level = first_stage;
>> +
>> + /* calculate the address width */
>> + addr_width = agaw_to_width(iommu->agaw);
>> + if (addr_width > cap_mgaw(iommu->cap))
>> + addr_width = cap_mgaw(iommu->cap);
>> + domain->gaw = addr_width;
>> + domain->agaw = iommu->agaw;
>> + domain->max_addr = __DOMAIN_MAX_ADDR(addr_width);
>> +
>> + /* iommu memory access coherency */
>> + domain->iommu_coherency = iommu_paging_structure_coherency(iommu);
>> +
>> + /* pagesize bitmap */
>> + domain->domain.pgsize_bitmap = SZ_4K;
>> + domain->iommu_superpage = iommu_superpage_capability(iommu, first_stage);
>> + domain->domain.pgsize_bitmap |= domain_super_pgsize_bitmap(domain);
> Then some of this stuff is really just paging only. Like
> SVA/identity/etc don't have pgszie and other things.

Yeah, good suggestion. I could do this in this series if it needs a new
version or in my next series which will add domain_alloc_paging for the
intel driver.

Best regards,
baolu