* [PATCH v3 1/6] lib: add ISO 3309 model crc64
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
@ 2024-05-30 12:24 ` kamlesh
2024-06-11 3:14 ` Eric Biggers
2024-05-30 12:24 ` [PATCH v3 2/6] crypto: crc64 - add crc64-iso3309 framework kamlesh
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: kamlesh @ 2024-05-30 12:24 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree, Kamlesh Gurudasani
From: Kamlesh Gurudasani <kamlesh@ti.com>
Add the polynomial to the crc64 table generation, and provide a
generic library routine implementing the algorithm.
64-bit cyclic redundancy checks (CRC) according to the ISO 3309:1991
standard.
The ISO 3309:1991 64-bit CRC model parameters are as follows:
Generator Polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial Value: 0x000000000000001B
Initial value: 0x0000000000000000
Reflected Input: False
Reflected Output: False
Xor Final: 0x0000000000000000
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
include/linux/crc64.h | 1 +
lib/crc64.c | 27 +++++++++++++++++++++++++++
lib/gen_crc64table.c | 6 ++++++
3 files changed, 34 insertions(+)
diff --git a/include/linux/crc64.h b/include/linux/crc64.h
index e044c60d1e61..b791316f251c 100644
--- a/include/linux/crc64.h
+++ b/include/linux/crc64.h
@@ -10,6 +10,7 @@
#define CRC64_ROCKSOFT_STRING "crc64-rocksoft"
u64 __pure crc64_be(u64 crc, const void *p, size_t len);
+u64 __pure crc64_iso3309_generic(u64 crc, const void *p, size_t len);
u64 __pure crc64_rocksoft_generic(u64 crc, const void *p, size_t len);
u64 crc64_rocksoft(const unsigned char *buffer, size_t len);
diff --git a/lib/crc64.c b/lib/crc64.c
index 61ae8dfb6a1c..40369dd26812 100644
--- a/lib/crc64.c
+++ b/lib/crc64.c
@@ -22,6 +22,11 @@
* x^24 + x^23 + x^22 + x^21 + x^19 + x^17 + x^13 + x^12 + x^10 + x^9 +
* x^7 + x^4 + x + 1
*
+ * crc64iso3309table[256] table is from the ISO-3309:1991 specification
+ * polynomial defined as,
+ *
+ * x^64 + x^4 + x^3 + x + 1
+ *
* crc64rocksoft[256] table is from the Rocksoft specification polynomial
* defined as,
*
@@ -63,6 +68,28 @@ u64 __pure crc64_be(u64 crc, const void *p, size_t len)
}
EXPORT_SYMBOL_GPL(crc64_be);
+/**
+ * crc64_iso3309_generic - Calculate bitwise ISO3309 CRC64
+ * @crc: seed value for computation. 0 for a new CRC calculation, or the
+ * previous crc64 value if computing incrementally.
+ * @p: pointer to buffer over which CRC64 is run
+ * @len: length of buffer @p
+ */
+u64 __pure crc64_iso3309_generic(u64 crc, const void *p, size_t len)
+{
+ size_t i, t;
+
+ const unsigned char *_p = p;
+
+ for (i = 0; i < len; i++) {
+ t = ((crc >> 56) ^ (*_p++)) & 0xFF;
+ crc = crc64iso3309table[t] ^ (crc << 8);
+ }
+
+ return crc;
+}
+EXPORT_SYMBOL_GPL(crc64_iso3309_generic);
+
/**
* crc64_rocksoft_generic - Calculate bitwise Rocksoft CRC64
* @crc: seed value for computation. 0 for a new CRC calculation, or the
diff --git a/lib/gen_crc64table.c b/lib/gen_crc64table.c
index 55e222acd0b8..abc860487463 100644
--- a/lib/gen_crc64table.c
+++ b/lib/gen_crc64table.c
@@ -17,9 +17,11 @@
#include <stdio.h>
#define CRC64_ECMA182_POLY 0x42F0E1EBA9EA3693ULL
+#define CRC64_ISO3309_POLY 0x000000000000001BULL
#define CRC64_ROCKSOFT_POLY 0x9A6C9329AC4BC9B5ULL
static uint64_t crc64_table[256] = {0};
+static uint64_t crc64_iso3309_table[256] = {0};
static uint64_t crc64_rocksoft_table[256] = {0};
static void generate_reflected_crc64_table(uint64_t table[256], uint64_t poly)
@@ -82,6 +84,9 @@ static void print_crc64_tables(void)
printf("static const u64 ____cacheline_aligned crc64table[256] = {\n");
output_table(crc64_table);
+ printf("\nstatic const u64 ____cacheline_aligned crc64iso3309table[256] = {\n");
+ output_table(crc64_iso3309_table);
+
printf("\nstatic const u64 ____cacheline_aligned crc64rocksofttable[256] = {\n");
output_table(crc64_rocksoft_table);
}
@@ -89,6 +94,7 @@ static void print_crc64_tables(void)
int main(int argc, char *argv[])
{
generate_crc64_table(crc64_table, CRC64_ECMA182_POLY);
+ generate_crc64_table(crc64_iso3309_table, CRC64_ISO3309_POLY);
generate_reflected_crc64_table(crc64_rocksoft_table, CRC64_ROCKSOFT_POLY);
print_crc64_tables();
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 1/6] lib: add ISO 3309 model crc64
2024-05-30 12:24 ` [PATCH v3 1/6] lib: add ISO 3309 model crc64 kamlesh
@ 2024-06-11 3:14 ` Eric Biggers
0 siblings, 0 replies; 16+ messages in thread
From: Eric Biggers @ 2024-06-11 3:14 UTC (permalink / raw)
To: kamlesh
Cc: herbert, kristo, will, akpm, davem, mcoquelin.stm32,
alexandre.torgue, robh, krzysztof.kozlowski+dt, conor+dt,
vigneshr, catalin.marinas, linux-kernel, linux-crypto,
linux-stm32, linux-arm-kernel, devicetree
On Thu, May 30, 2024 at 05:54:23PM +0530, kamlesh@ti.com wrote:
> diff --git a/lib/crc64.c b/lib/crc64.c
> index 61ae8dfb6a1c..40369dd26812 100644
> --- a/lib/crc64.c
> +++ b/lib/crc64.c
> @@ -22,6 +22,11 @@
> * x^24 + x^23 + x^22 + x^21 + x^19 + x^17 + x^13 + x^12 + x^10 + x^9 +
> * x^7 + x^4 + x + 1
> *
> + * crc64iso3309table[256] table is from the ISO-3309:1991 specification
> + * polynomial defined as,
> + *
> + * x^64 + x^4 + x^3 + x + 1
> + *
> * crc64rocksoft[256] table is from the Rocksoft specification polynomial
> * defined as,
> *
> @@ -63,6 +68,28 @@ u64 __pure crc64_be(u64 crc, const void *p, size_t len)
> }
> EXPORT_SYMBOL_GPL(crc64_be);
>
> +/**
> + * crc64_iso3309_generic - Calculate bitwise ISO3309 CRC64
> + * @crc: seed value for computation. 0 for a new CRC calculation, or the
> + * previous crc64 value if computing incrementally.
> + * @p: pointer to buffer over which CRC64 is run
> + * @len: length of buffer @p
> + */
> +u64 __pure crc64_iso3309_generic(u64 crc, const void *p, size_t len)
> +{
> + size_t i, t;
> +
> + const unsigned char *_p = p;
> +
> + for (i = 0; i < len; i++) {
> + t = ((crc >> 56) ^ (*_p++)) & 0xFF;
> + crc = crc64iso3309table[t] ^ (crc << 8);
> + }
> +
> + return crc;
> +}
> +EXPORT_SYMBOL_GPL(crc64_iso3309_generic);
Putting this in lib/ seems premature, given that this is only used by
crypto/crc64_iso3309_generic.c.
- Eric
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/6] crypto: crc64 - add crc64-iso3309 framework
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
2024-05-30 12:24 ` [PATCH v3 1/6] lib: add ISO 3309 model crc64 kamlesh
@ 2024-05-30 12:24 ` kamlesh
2024-05-30 12:24 ` [PATCH v3 3/6] dt-bindings: crypto: Add Texas Instruments MCRC64 kamlesh
` (4 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: kamlesh @ 2024-05-30 12:24 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree, Kamlesh Gurudasani
From: Kamlesh Gurudasani <kamlesh@ti.com>
Hardware specific features may be able to calculate a crc64-iso3309,
so provide a framework for drivers to register their implementation.
If nothing is registered, fallback to the generic table lookup
implementation. The implementation is modeled after the crc64-rocksoft
equivalent.
Add testmgr, tcrypt tests and vectors for 64-bit cyclic
redundancy checks (CRC) according to the ISO 3309 standard.
The ISO 3309 64-bit CRC model parameters are as follows:
Generator Polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial Value: 0x000000000000001B
Initial value: 0x0000000000000000
Reflected Input: False
Reflected Output: False
Xor Final: 0x0000000000000000
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
crypto/Kconfig | 11 +++
crypto/Makefile | 1 +
crypto/crc64_iso3309_generic.c | 119 +++++++++++++++++++++++++++
crypto/tcrypt.c | 6 ++
crypto/testmgr.c | 7 ++
crypto/testmgr.h | 404 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/crc64.h | 1 +
7 files changed, 549 insertions(+)
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 5688d42a59c2..125cc88805ae 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -1124,6 +1124,17 @@ config CRYPTO_CRCT10DIF
CRC algorithm used by the SCSI Block Commands standard.
+config CRYPTO_CRC64_ISO3309
+ tristate "CRC64 based on ISO 3309 Model algorithm"
+ depends on CRC64
+ select CRYPTO_HASH
+ help
+ CRC64 CRC algorithm based on the ISO 3309 Model CRC Algorithm
+
+ Generator polynomial: x^64 + x^4 + x^3 + x + 1
+ Polynomial value: 0x000000000000001b
+ See https://en.wikipedia.org/wiki/Cyclic_redundancy_check
+
config CRYPTO_CRC64_ROCKSOFT
tristate "CRC64 based on Rocksoft Model algorithm"
depends on CRC64
diff --git a/crypto/Makefile b/crypto/Makefile
index de9a3312a2c8..4d419e5fb379 100644
--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -158,6 +158,7 @@ obj-$(CONFIG_CRYPTO_MICHAEL_MIC) += michael_mic.o
obj-$(CONFIG_CRYPTO_CRC32C) += crc32c_generic.o
obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o
obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o
+obj-$(CONFIG_CRYPTO_CRC64_ISO3309) += crc64_iso3309_generic.o
obj-$(CONFIG_CRYPTO_CRC64_ROCKSOFT) += crc64_rocksoft_generic.o
obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o
obj-$(CONFIG_CRYPTO_LZO) += lzo.o lzo-rle.o
diff --git a/crypto/crc64_iso3309_generic.c b/crypto/crc64_iso3309_generic.c
new file mode 100644
index 000000000000..8fcc092de787
--- /dev/null
+++ b/crypto/crc64_iso3309_generic.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/crc64.h>
+#include <linux/module.h>
+#include <crypto/internal/hash.h>
+#include <asm/unaligned.h>
+
+static int chksum_cra_init(struct crypto_tfm *tfm)
+{
+ u64 *key = crypto_tfm_ctx(tfm);
+
+ *key = 0;
+ return 0;
+}
+
+static int chksum_init(struct shash_desc *desc)
+{
+ u64 *key = crypto_shash_ctx(desc->tfm);
+ u64 *crc = shash_desc_ctx(desc);
+
+ *crc = *key;
+ return 0;
+}
+
+static int chksum_update(struct shash_desc *desc, const u8 *data,
+ unsigned int length)
+{
+ u64 *crc = shash_desc_ctx(desc);
+
+ *crc = crc64_iso3309_generic(*crc, data, length);
+ return 0;
+}
+
+static int chksum_final(struct shash_desc *desc, u8 *out)
+{
+ u64 *crc = shash_desc_ctx(desc);
+
+ put_unaligned_le64(*crc, out);
+ return 0;
+}
+
+static int __chksum_finup(u64 crc, const u8 *data, unsigned int len, u8 *out)
+{
+ crc = crc64_iso3309_generic(crc, data, len);
+
+ put_unaligned_le64(crc, out);
+ return 0;
+}
+
+static int chksum_finup(struct shash_desc *desc, const u8 *data,
+ unsigned int len, u8 *out)
+{
+ u64 *crc = shash_desc_ctx(desc);
+
+ return __chksum_finup(*crc, data, len, out);
+}
+
+static int chksum_digest(struct shash_desc *desc, const u8 *data,
+ unsigned int length, u8 *out)
+{
+ u64 *key = crypto_shash_ctx(desc->tfm);
+
+ return __chksum_finup(*key, data, length, out);
+}
+
+/*
+ * Setting the seed allows arbitrary accumulators and flexible XOR policy
+ */
+static int chksum_setkey(struct crypto_shash *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ u64 *mctx = crypto_shash_ctx(tfm);
+
+ if (keylen != sizeof(u64))
+ return -EINVAL;
+
+ *mctx = get_unaligned_le64(key);
+ return 0;
+}
+
+static struct shash_alg alg = {
+ .digestsize = sizeof(u64),
+ .setkey = chksum_setkey,
+ .init = chksum_init,
+ .update = chksum_update,
+ .final = chksum_final,
+ .finup = chksum_finup,
+ .digest = chksum_digest,
+ .descsize = sizeof(u64),
+ .base = {
+ .cra_name = CRC64_ISO3309_STRING,
+ .cra_driver_name = "crc64-iso3309-generic",
+ .cra_priority = 200,
+ .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
+ .cra_blocksize = 1,
+ .cra_ctxsize = sizeof(u64),
+ .cra_module = THIS_MODULE,
+ .cra_init = chksum_cra_init,
+ }
+};
+
+static int __init crc64_iso3309_init(void)
+{
+ return crypto_register_shash(&alg);
+}
+
+static void __exit crc64_iso3309_exit(void)
+{
+ crypto_unregister_shash(&alg);
+}
+
+module_init(crc64_iso3309_init);
+module_exit(crc64_iso3309_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh@ti.com>");
+MODULE_DESCRIPTION("ISO3309 model CRC64 calculation");
+MODULE_ALIAS_CRYPTO("crc64-iso3309");
+MODULE_ALIAS_CRYPTO("crc64-iso3309-generic");
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 8aea416f6480..efc76dd9f57f 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -2314,6 +2314,12 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
generic_hash_speed_template);
if (mode > 300 && mode < 400) break;
fallthrough;
+ case 329:
+ test_hash_speed("crc64-iso3309", sec,
+ generic_hash_speed_template);
+ if (mode > 300 && mode < 400)
+ break;
+ fallthrough;
case 399:
break;
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 00f5a6cf341a..d6ae74efca98 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -4656,6 +4656,13 @@ static const struct alg_test_desc alg_test_descs[] = {
.suite = {
.hash = __VECS(crc32c_tv_template)
}
+ }, {
+ .alg = "crc64-iso3309",
+ .test = alg_test_hash,
+ .fips_allowed = 1,
+ .suite = {
+ .hash = __VECS(crc64_iso3309_tv_template)
+ }
}, {
.alg = "crc64-rocksoft",
.test = alg_test_hash,
diff --git a/crypto/testmgr.h b/crypto/testmgr.h
index 5350cfd9d325..21387e405e71 100644
--- a/crypto/testmgr.h
+++ b/crypto/testmgr.h
@@ -5355,6 +5355,410 @@ static const struct hash_testvec rmd160_tv_template[] = {
}
};
+static const struct hash_testvec crc64_iso3309_tv_template[] = {
+ {
+ .psize = 0,
+ .digest = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ },
+ {
+ .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25\x26\x27\x28",
+ .psize = 40,
+ .digest = "\xaf\x45\xba\x7d\xf2\xda\xa0\xaa",
+ },
+ {
+ .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50",
+ .psize = 40,
+ .digest = "\x81\x55\x2e\x76\xf8\xd0\xaa\xa0",
+ },
+ {
+ .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78",
+ .psize = 40,
+ .digest = "\xc6\xb6\x26\x82\x0d\x25\x5f\x55",
+ },
+ {
+ .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0",
+ .psize = 40,
+ .digest = "\x20\x8a\xe6\x59\xdf\xf7\x8d\x87",
+ },
+ {
+ .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8",
+ .psize = 40,
+ .digest = "\x19\x9e\xba\xff\x70\x58\x22\x28",
+
+ },
+ {
+ .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
+ .psize = 40,
+ .digest = "\xa3\xdc\x11\x98\x16\x3e\x44\x4e",
+ },
+ {
+ .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50",
+ .psize = 40,
+ .digest = "\x81\x55\x2e\x76\xf8\xd0\xaa\xa0",
+ },
+ {
+ .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78",
+ .psize = 40,
+ .digest = "\xc6\xb6\x26\x82\x0d\x25\x5f\x55",
+ },
+ {
+ .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0",
+ .psize = 40,
+ .digest = "\x20\x8a\xe6\x59\xdf\xf7\x8d\x87",
+ },
+ {
+ .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8",
+ .psize = 40,
+ .digest = "\x19\x9e\xba\xff\x70\x58\x22\x28",
+ },
+ {
+ .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
+ .psize = 40,
+ .digest = "\xa3\xdc\x11\x98\x16\x3e\x44\x4e",
+ },
+ {
+ .key = "\xff\xff\xff\xff\xff\xff\xff\xff",
+ .ksize = 8,
+ .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25\x26\x27\x28"
+ "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50"
+ "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78"
+ "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0"
+ "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8"
+ "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
+ .psize = 240,
+ .digest = "\x8b\xa6\xd7\x91\xb4\x74\x96\x84",
+ }, {
+ .key = "\xff\xff\xff\xff\xff\xff\xff\xff",
+ .ksize = 8,
+ .plaintext = "\x6e\x05\x79\x10\xa7\x1b\xb2\x49"
+ "\xe0\x54\xeb\x82\x19\x8d\x24\xbb"
+ "\x2f\xc6\x5d\xf4\x68\xff\x96\x0a"
+ "\xa1\x38\xcf\x43\xda\x71\x08\x7c"
+ "\x13\xaa\x1e\xb5\x4c\xe3\x57\xee"
+ "\x85\x1c\x90\x27\xbe\x32\xc9\x60"
+ "\xf7\x6b\x02\x99\x0d\xa4\x3b\xd2"
+ "\x46\xdd\x74\x0b\x7f\x16\xad\x21"
+ "\xb8\x4f\xe6\x5a\xf1\x88\x1f\x93"
+ "\x2a\xc1\x35\xcc\x63\xfa\x6e\x05"
+ "\x9c\x10\xa7\x3e\xd5\x49\xe0\x77"
+ "\x0e\x82\x19\xb0\x24\xbb\x52\xe9"
+ "\x5d\xf4\x8b\x22\x96\x2d\xc4\x38"
+ "\xcf\x66\xfd\x71\x08\x9f\x13\xaa"
+ "\x41\xd8\x4c\xe3\x7a\x11\x85\x1c"
+ "\xb3\x27\xbe\x55\xec\x60\xf7\x8e"
+ "\x02\x99\x30\xc7\x3b\xd2\x69\x00"
+ "\x74\x0b\xa2\x16\xad\x44\xdb\x4f"
+ "\xe6\x7d\x14\x88\x1f\xb6\x2a\xc1"
+ "\x58\xef\x63\xfa\x91\x05\x9c\x33"
+ "\xca\x3e\xd5\x6c\x03\x77\x0e\xa5"
+ "\x19\xb0\x47\xde\x52\xe9\x80\x17"
+ "\x8b\x22\xb9\x2d\xc4\x5b\xf2\x66"
+ "\xfd\x94\x08\x9f\x36\xcd\x41\xd8"
+ "\x6f\x06\x7a\x11\xa8\x1c\xb3\x4a"
+ "\xe1\x55\xec\x83\x1a\x8e\x25\xbc"
+ "\x30\xc7\x5e\xf5\x69\x00\x97\x0b"
+ "\xa2\x39\xd0\x44\xdb\x72\x09\x7d"
+ "\x14\xab\x1f\xb6\x4d\xe4\x58\xef"
+ "\x86\x1d\x91\x28\xbf\x33\xca\x61"
+ "\xf8\x6c\x03\x9a\x0e\xa5\x3c\xd3"
+ "\x47\xde\x75\x0c\x80\x17\xae\x22"
+ "\xb9\x50\xe7\x5b\xf2\x89\x20\x94"
+ "\x2b\xc2\x36\xcd\x64\xfb\x6f\x06"
+ "\x9d\x11\xa8\x3f\xd6\x4a\xe1\x78"
+ "\x0f\x83\x1a\xb1\x25\xbc\x53\xea"
+ "\x5e\xf5\x8c\x00\x97\x2e\xc5\x39"
+ "\xd0\x67\xfe\x72\x09\xa0\x14\xab"
+ "\x42\xd9\x4d\xe4\x7b\x12\x86\x1d"
+ "\xb4\x28\xbf\x56\xed\x61\xf8\x8f"
+ "\x03\x9a\x31\xc8\x3c\xd3\x6a\x01"
+ "\x75\x0c\xa3\x17\xae\x45\xdc\x50"
+ "\xe7\x7e\x15\x89\x20\xb7\x2b\xc2"
+ "\x59\xf0\x64\xfb\x92\x06\x9d\x34"
+ "\xcb\x3f\xd6\x6d\x04\x78\x0f\xa6"
+ "\x1a\xb1\x48\xdf\x53\xea\x81\x18"
+ "\x8c\x23\xba\x2e\xc5\x5c\xf3\x67"
+ "\xfe\x95\x09\xa0\x37\xce\x42\xd9"
+ "\x70\x07\x7b\x12\xa9\x1d\xb4\x4b"
+ "\xe2\x56\xed\x84\x1b\x8f\x26\xbd"
+ "\x31\xc8\x5f\xf6\x6a\x01\x98\x0c"
+ "\xa3\x3a\xd1\x45\xdc\x73\x0a\x7e"
+ "\x15\xac\x20\xb7\x4e\xe5\x59\xf0"
+ "\x87\x1e\x92\x29\xc0\x34\xcb\x62"
+ "\xf9\x6d\x04\x9b\x0f\xa6\x3d\xd4"
+ "\x48\xdf\x76\x0d\x81\x18\xaf\x23"
+ "\xba\x51\xe8\x5c\xf3\x8a\x21\x95"
+ "\x2c\xc3\x37\xce\x65\xfc\x70\x07"
+ "\x9e\x12\xa9\x40\xd7\x4b\xe2\x79"
+ "\x10\x84\x1b\xb2\x26\xbd\x54\xeb"
+ "\x5f\xf6\x8d\x01\x98\x2f\xc6\x3a"
+ "\xd1\x68\xff\x73\x0a\xa1\x15\xac"
+ "\x43\xda\x4e\xe5\x7c\x13\x87\x1e"
+ "\xb5\x29\xc0\x57\xee\x62\xf9\x90"
+ "\x04\x9b\x32\xc9\x3d\xd4\x6b\x02"
+ "\x76\x0d\xa4\x18\xaf\x46\xdd\x51"
+ "\xe8\x7f\x16\x8a\x21\xb8\x2c\xc3"
+ "\x5a\xf1\x65\xfc\x93\x07\x9e\x35"
+ "\xcc\x40\xd7\x6e\x05\x79\x10\xa7"
+ "\x1b\xb2\x49\xe0\x54\xeb\x82\x19"
+ "\x8d\x24\xbb\x2f\xc6\x5d\xf4\x68"
+ "\xff\x96\x0a\xa1\x38\xcf\x43\xda"
+ "\x71\x08\x7c\x13\xaa\x1e\xb5\x4c"
+ "\xe3\x57\xee\x85\x1c\x90\x27\xbe"
+ "\x32\xc9\x60\xf7\x6b\x02\x99\x0d"
+ "\xa4\x3b\xd2\x46\xdd\x74\x0b\x7f"
+ "\x16\xad\x21\xb8\x4f\xe6\x5a\xf1"
+ "\x88\x1f\x93\x2a\xc1\x35\xcc\x63"
+ "\xfa\x6e\x05\x9c\x10\xa7\x3e\xd5"
+ "\x49\xe0\x77\x0e\x82\x19\xb0\x24"
+ "\xbb\x52\xe9\x5d\xf4\x8b\x22\x96"
+ "\x2d\xc4\x38\xcf\x66\xfd\x71\x08"
+ "\x9f\x13\xaa\x41\xd8\x4c\xe3\x7a"
+ "\x11\x85\x1c\xb3\x27\xbe\x55\xec"
+ "\x60\xf7\x8e\x02\x99\x30\xc7\x3b"
+ "\xd2\x69\x00\x74\x0b\xa2\x16\xad"
+ "\x44\xdb\x4f\xe6\x7d\x14\x88\x1f"
+ "\xb6\x2a\xc1\x58\xef\x63\xfa\x91"
+ "\x05\x9c\x33\xca\x3e\xd5\x6c\x03"
+ "\x77\x0e\xa5\x19\xb0\x47\xde\x52"
+ "\xe9\x80\x17\x8b\x22\xb9\x2d\xc4"
+ "\x5b\xf2\x66\xfd\x94\x08\x9f\x36"
+ "\xcd\x41\xd8\x6f\x06\x7a\x11\xa8"
+ "\x1c\xb3\x4a\xe1\x55\xec\x83\x1a"
+ "\x8e\x25\xbc\x30\xc7\x5e\xf5\x69"
+ "\x00\x97\x0b\xa2\x39\xd0\x44\xdb"
+ "\x72\x09\x7d\x14\xab\x1f\xb6\x4d"
+ "\xe4\x58\xef\x86\x1d\x91\x28\xbf"
+ "\x33\xca\x61\xf8\x6c\x03\x9a\x0e"
+ "\xa5\x3c\xd3\x47\xde\x75\x0c\x80"
+ "\x17\xae\x22\xb9\x50\xe7\x5b\xf2"
+ "\x89\x20\x94\x2b\xc2\x36\xcd\x64"
+ "\xfb\x6f\x06\x9d\x11\xa8\x3f\xd6"
+ "\x4a\xe1\x78\x0f\x83\x1a\xb1\x25"
+ "\xbc\x53\xea\x5e\xf5\x8c\x00\x97"
+ "\x2e\xc5\x39\xd0\x67\xfe\x72\x09"
+ "\xa0\x14\xab\x42\xd9\x4d\xe4\x7b"
+ "\x12\x86\x1d\xb4\x28\xbf\x56\xed"
+ "\x61\xf8\x8f\x03\x9a\x31\xc8\x3c"
+ "\xd3\x6a\x01\x75\x0c\xa3\x17\xae"
+ "\x45\xdc\x50\xe7\x7e\x15\x89\x20"
+ "\xb7\x2b\xc2\x59\xf0\x64\xfb\x92"
+ "\x06\x9d\x34\xcb\x3f\xd6\x6d\x04"
+ "\x78\x0f\xa6\x1a\xb1\x48\xdf\x53"
+ "\xea\x81\x18\x8c\x23\xba\x2e\xc5"
+ "\x5c\xf3\x67\xfe\x95\x09\xa0\x37"
+ "\xce\x42\xd9\x70\x07\x7b\x12\xa9"
+ "\x1d\xb4\x4b\xe2\x56\xed\x84\x1b"
+ "\x8f\x26\xbd\x31\xc8\x5f\xf6\x6a"
+ "\x01\x98\x0c\xa3\x3a\xd1\x45\xdc"
+ "\x73\x0a\x7e\x15\xac\x20\xb7\x4e"
+ "\xe5\x59\xf0\x87\x1e\x92\x29\xc0"
+ "\x34\xcb\x62\xf9\x6d\x04\x9b\x0f"
+ "\xa6\x3d\xd4\x48\xdf\x76\x0d\x81"
+ "\x18\xaf\x23\xba\x51\xe8\x5c\xf3"
+ "\x8a\x21\x95\x2c\xc3\x37\xce\x65"
+ "\xfc\x70\x07\x9e\x12\xa9\x40\xd7"
+ "\x4b\xe2\x79\x10\x84\x1b\xb2\x26"
+ "\xbd\x54\xeb\x5f\xf6\x8d\x01\x98"
+ "\x2f\xc6\x3a\xd1\x68\xff\x73\x0a"
+ "\xa1\x15\xac\x43\xda\x4e\xe5\x7c"
+ "\x13\x87\x1e\xb5\x29\xc0\x57\xee"
+ "\x62\xf9\x90\x04\x9b\x32\xc9\x3d"
+ "\xd4\x6b\x02\x76\x0d\xa4\x18\xaf"
+ "\x46\xdd\x51\xe8\x7f\x16\x8a\x21"
+ "\xb8\x2c\xc3\x5a\xf1\x65\xfc\x93"
+ "\x07\x9e\x35\xcc\x40\xd7\x6e\x05"
+ "\x79\x10\xa7\x1b\xb2\x49\xe0\x54"
+ "\xeb\x82\x19\x8d\x24\xbb\x2f\xc6"
+ "\x5d\xf4\x68\xff\x96\x0a\xa1\x38"
+ "\xcf\x43\xda\x71\x08\x7c\x13\xaa"
+ "\x1e\xb5\x4c\xe3\x57\xee\x85\x1c"
+ "\x90\x27\xbe\x32\xc9\x60\xf7\x6b"
+ "\x02\x99\x0d\xa4\x3b\xd2\x46\xdd"
+ "\x74\x0b\x7f\x16\xad\x21\xb8\x4f"
+ "\xe6\x5a\xf1\x88\x1f\x93\x2a\xc1"
+ "\x35\xcc\x63\xfa\x6e\x05\x9c\x10"
+ "\xa7\x3e\xd5\x49\xe0\x77\x0e\x82"
+ "\x19\xb0\x24\xbb\x52\xe9\x5d\xf4"
+ "\x8b\x22\x96\x2d\xc4\x38\xcf\x66"
+ "\xfd\x71\x08\x9f\x13\xaa\x41\xd8"
+ "\x4c\xe3\x7a\x11\x85\x1c\xb3\x27"
+ "\xbe\x55\xec\x60\xf7\x8e\x02\x99"
+ "\x30\xc7\x3b\xd2\x69\x00\x74\x0b"
+ "\xa2\x16\xad\x44\xdb\x4f\xe6\x7d"
+ "\x14\x88\x1f\xb6\x2a\xc1\x58\xef"
+ "\x63\xfa\x91\x05\x9c\x33\xca\x3e"
+ "\xd5\x6c\x03\x77\x0e\xa5\x19\xb0"
+ "\x47\xde\x52\xe9\x80\x17\x8b\x22"
+ "\xb9\x2d\xc4\x5b\xf2\x66\xfd\x94"
+ "\x08\x9f\x36\xcd\x41\xd8\x6f\x06"
+ "\x7a\x11\xa8\x1c\xb3\x4a\xe1\x55"
+ "\xec\x83\x1a\x8e\x25\xbc\x30\xc7"
+ "\x5e\xf5\x69\x00\x97\x0b\xa2\x39"
+ "\xd0\x44\xdb\x72\x09\x7d\x14\xab"
+ "\x1f\xb6\x4d\xe4\x58\xef\x86\x1d"
+ "\x91\x28\xbf\x33\xca\x61\xf8\x6c"
+ "\x03\x9a\x0e\xa5\x3c\xd3\x47\xde"
+ "\x75\x0c\x80\x17\xae\x22\xb9\x50"
+ "\xe7\x5b\xf2\x89\x20\x94\x2b\xc2"
+ "\x36\xcd\x64\xfb\x6f\x06\x9d\x11"
+ "\xa8\x3f\xd6\x4a\xe1\x78\x0f\x83"
+ "\x1a\xb1\x25\xbc\x53\xea\x5e\xf5"
+ "\x8c\x00\x97\x2e\xc5\x39\xd0\x67"
+ "\xfe\x72\x09\xa0\x14\xab\x42\xd9"
+ "\x4d\xe4\x7b\x12\x86\x1d\xb4\x28"
+ "\xbf\x56\xed\x61\xf8\x8f\x03\x9a"
+ "\x31\xc8\x3c\xd3\x6a\x01\x75\x0c"
+ "\xa3\x17\xae\x45\xdc\x50\xe7\x7e"
+ "\x15\x89\x20\xb7\x2b\xc2\x59\xf0"
+ "\x64\xfb\x92\x06\x9d\x34\xcb\x3f"
+ "\xd6\x6d\x04\x78\x0f\xa6\x1a\xb1"
+ "\x48\xdf\x53\xea\x81\x18\x8c\x23"
+ "\xba\x2e\xc5\x5c\xf3\x67\xfe\x95"
+ "\x09\xa0\x37\xce\x42\xd9\x70\x07"
+ "\x7b\x12\xa9\x1d\xb4\x4b\xe2\x56"
+ "\xed\x84\x1b\x8f\x26\xbd\x31\xc8"
+ "\x5f\xf6\x6a\x01\x98\x0c\xa3\x3a"
+ "\xd1\x45\xdc\x73\x0a\x7e\x15\xac"
+ "\x20\xb7\x4e\xe5\x59\xf0\x87\x1e"
+ "\x92\x29\xc0\x34\xcb\x62\xf9\x6d"
+ "\x04\x9b\x0f\xa6\x3d\xd4\x48\xdf"
+ "\x76\x0d\x81\x18\xaf\x23\xba\x51"
+ "\xe8\x5c\xf3\x8a\x21\x95\x2c\xc3"
+ "\x37\xce\x65\xfc\x70\x07\x9e\x12"
+ "\xa9\x40\xd7\x4b\xe2\x79\x10\x84"
+ "\x1b\xb2\x26\xbd\x54\xeb\x5f\xf6"
+ "\x8d\x01\x98\x2f\xc6\x3a\xd1\x68"
+ "\xff\x73\x0a\xa1\x15\xac\x43\xda"
+ "\x4e\xe5\x7c\x13\x87\x1e\xb5\x29"
+ "\xc0\x57\xee\x62\xf9\x90\x04\x9b"
+ "\x32\xc9\x3d\xd4\x6b\x02\x76\x0d"
+ "\xa4\x18\xaf\x46\xdd\x51\xe8\x7f"
+ "\x16\x8a\x21\xb8\x2c\xc3\x5a\xf1"
+ "\x65\xfc\x93\x07\x9e\x35\xcc\x40"
+ "\xd7\x6e\x05\x79\x10\xa7\x1b\xb2"
+ "\x49\xe0\x54\xeb\x82\x19\x8d\x24"
+ "\xbb\x2f\xc6\x5d\xf4\x68\xff\x96"
+ "\x0a\xa1\x38\xcf\x43\xda\x71\x08"
+ "\x7c\x13\xaa\x1e\xb5\x4c\xe3\x57"
+ "\xee\x85\x1c\x90\x27\xbe\x32\xc9"
+ "\x60\xf7\x6b\x02\x99\x0d\xa4\x3b"
+ "\xd2\x46\xdd\x74\x0b\x7f\x16\xad"
+ "\x21\xb8\x4f\xe6\x5a\xf1\x88\x1f"
+ "\x93\x2a\xc1\x35\xcc\x63\xfa\x6e"
+ "\x05\x9c\x10\xa7\x3e\xd5\x49\xe0"
+ "\x77\x0e\x82\x19\xb0\x24\xbb\x52"
+ "\xe9\x5d\xf4\x8b\x22\x96\x2d\xc4"
+ "\x38\xcf\x66\xfd\x71\x08\x9f\x13"
+ "\xaa\x41\xd8\x4c\xe3\x7a\x11\x85"
+ "\x1c\xb3\x27\xbe\x55\xec\x60\xf7"
+ "\x8e\x02\x99\x30\xc7\x3b\xd2\x69"
+ "\x00\x74\x0b\xa2\x16\xad\x44\xdb"
+ "\x4f\xe6\x7d\x14\x88\x1f\xb6\x2a"
+ "\xc1\x58\xef\x63\xfa\x91\x05\x9c"
+ "\x33\xca\x3e\xd5\x6c\x03\x77\x0e"
+ "\xa5\x19\xb0\x47\xde\x52\xe9\x80"
+ "\x17\x8b\x22\xb9\x2d\xc4\x5b\xf2"
+ "\x66\xfd\x94\x08\x9f\x36\xcd\x41"
+ "\xd8\x6f\x06\x7a\x11\xa8\x1c\xb3"
+ "\x4a\xe1\x55\xec\x83\x1a\x8e\x25"
+ "\xbc\x30\xc7\x5e\xf5\x69\x00\x97"
+ "\x0b\xa2\x39\xd0\x44\xdb\x72\x09"
+ "\x7d\x14\xab\x1f\xb6\x4d\xe4\x58"
+ "\xef\x86\x1d\x91\x28\xbf\x33\xca"
+ "\x61\xf8\x6c\x03\x9a\x0e\xa5\x3c"
+ "\xd3\x47\xde\x75\x0c\x80\x17\xae"
+ "\x22\xb9\x50\xe7\x5b\xf2\x89\x20"
+ "\x94\x2b\xc2\x36\xcd\x64\xfb\x6f"
+ "\x06\x9d\x11\xa8\x3f\xd6\x4a\xe1"
+ "\x78\x0f\x83\x1a\xb1\x25\xbc\x53"
+ "\xea\x5e\xf5\x8c\x00\x97\x2e\xc5"
+ "\x39\xd0\x67\xfe\x72\x09\xa0\x14"
+ "\xab\x42\xd9\x4d\xe4\x7b\x12\x86"
+ "\x1d\xb4\x28\xbf\x56\xed\x61\xf8"
+ "\x8f\x03\x9a\x31\xc8\x3c\xd3\x6a"
+ "\x01\x75\x0c\xa3\x17\xae\x45\xdc"
+ "\x50\xe7\x7e\x15\x89\x20\xb7\x2b"
+ "\xc2\x59\xf0\x64\xfb\x92\x06\x9d"
+ "\x34\xcb\x3f\xd6\x6d\x04\x78\x0f"
+ "\xa6\x1a\xb1\x48\xdf\x53\xea\x81"
+ "\x18\x8c\x23\xba\x2e\xc5\x5c\xf3"
+ "\x67\xfe\x95\x09\xa0\x37\xce\x42"
+ "\xd9\x70\x07\x7b\x12\xa9\x1d\xb4"
+ "\x4b\xe2\x56\xed\x84\x1b\x8f\x26"
+ "\xbd\x31\xc8\x5f\xf6\x6a\x01\x98",
+ .psize = 2048,
+ .digest = "\x4b\x82\xa5\x0e\x72\x01\x0b\xc6",
+ }
+};
+
static const u8 zeroes[4096] = { [0 ... 4095] = 0 };
static const u8 ones[4096] = { [0 ... 4095] = 0xff };
diff --git a/include/linux/crc64.h b/include/linux/crc64.h
index b791316f251c..890959372633 100644
--- a/include/linux/crc64.h
+++ b/include/linux/crc64.h
@@ -7,6 +7,7 @@
#include <linux/types.h>
+#define CRC64_ISO3309_STRING "crc64-iso3309"
#define CRC64_ROCKSOFT_STRING "crc64-rocksoft"
u64 __pure crc64_be(u64 crc, const void *p, size_t len);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 3/6] dt-bindings: crypto: Add Texas Instruments MCRC64
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
2024-05-30 12:24 ` [PATCH v3 1/6] lib: add ISO 3309 model crc64 kamlesh
2024-05-30 12:24 ` [PATCH v3 2/6] crypto: crc64 - add crc64-iso3309 framework kamlesh
@ 2024-05-30 12:24 ` kamlesh
2024-05-31 9:02 ` Krzysztof Kozlowski
2024-05-30 12:24 ` [PATCH v3 4/6] crypto: ti - add driver for MCRC64 engine kamlesh
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: kamlesh @ 2024-05-30 12:24 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree, Kamlesh Gurudasani
From: Kamlesh Gurudasani <kamlesh@ti.com>
Add binding for Texas Instruments MCRC64
MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
according to the ISO 3309 standard.
The ISO 3309 64-bit CRC model parameters are as follows:
Generator Polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial Value: 0x000000000000001B
Initial value: 0x0000000000000000
Reflected Input: False
Reflected Output: False
Xor Final: 0x0000000000000000
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
MAINTAINERS | 5 +++++
2 files changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
new file mode 100644
index 000000000000..52505cc40a57
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments MCRC64
+
+description:
+ The MCRC64 engine calculates 64-bit cyclic redundancy checks
+ (CRC) according to the ISO 3309 standard.
+
+maintainers:
+ - Kamlesh Gurudasani <kamlesh@ti.com>
+
+properties:
+ compatible:
+ const: ti,am62-mcrc64
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ crc@30300000 {
+ compatible = "ti,am62-mcrc64";
+ reg = <0x30300000 0x1000>;
+ clocks = <&k3_clks 116 0>;
+ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 613604d2e999..0c6bd9c22b91 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22191,6 +22191,11 @@ S: Maintained
F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml
F: drivers/iio/adc/ti-lmp92064.c
+TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER
+M: Kamlesh Gurudasani <kamlesh@ti.com>
+S: Maintained
+F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
+
TI PCM3060 ASoC CODEC DRIVER
M: Kirill Marinushkin <kmarinushkin@birdec.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 3/6] dt-bindings: crypto: Add Texas Instruments MCRC64
2024-05-30 12:24 ` [PATCH v3 3/6] dt-bindings: crypto: Add Texas Instruments MCRC64 kamlesh
@ 2024-05-31 9:02 ` Krzysztof Kozlowski
0 siblings, 0 replies; 16+ messages in thread
From: Krzysztof Kozlowski @ 2024-05-31 9:02 UTC (permalink / raw)
To: kamlesh, herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree
On 30/05/2024 14:24, kamlesh@ti.com wrote:
> From: Kamlesh Gurudasani <kamlesh@ti.com>
>
> Add binding for Texas Instruments MCRC64
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 4/6] crypto: ti - add driver for MCRC64 engine
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
` (2 preceding siblings ...)
2024-05-30 12:24 ` [PATCH v3 3/6] dt-bindings: crypto: Add Texas Instruments MCRC64 kamlesh
@ 2024-05-30 12:24 ` kamlesh
2024-06-11 12:02 ` Markus Elfring
2024-05-30 12:24 ` [PATCH v3 5/6 DONOTMERGE] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64 kamlesh
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: kamlesh @ 2024-05-30 12:24 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree, Kamlesh Gurudasani
From: Kamlesh Gurudasani <kamlesh@ti.com>
Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode.
In Full-CPU mode, the CPU does the data patterns transfer and signature
verification all by itself, only CRC calculation is being done by MCRC64
engine.
MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
according to the ISO 3309 standard.
The ISO 3309 64-bit CRC model parameters are as follows:
Generator Polynomial: x^64 + x^4 + x^3 + x + 1
Polynomial Value: 0x000000000000001B
Initial value: 0x0000000000000000
Reflected Input: False
Reflected Output: False
Xor Final: 0x0000000000000000
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
MAINTAINERS | 2 +
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
drivers/crypto/ti/Kconfig | 11 +++
drivers/crypto/ti/Makefile | 2 +
drivers/crypto/ti/mcrc64.c | 442 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
6 files changed, 459 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c6bd9c22b91..d072b5a0154f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22193,8 +22193,10 @@ F: drivers/iio/adc/ti-lmp92064.c
TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER
M: Kamlesh Gurudasani <kamlesh@ti.com>
+L: linux-crypto@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml
+F: drivers/crypto/ti/mcrc64.c
TI PCM3060 ASoC CODEC DRIVER
M: Kirill Marinushkin <kmarinushkin@birdec.com>
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index bb27690f8f7c..7e8ad3dc18da 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -806,5 +806,6 @@ config CRYPTO_DEV_SA2UL
source "drivers/crypto/aspeed/Kconfig"
source "drivers/crypto/starfive/Kconfig"
+source "drivers/crypto/ti/Kconfig"
endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index ad4ccef67d12..07488b610bed 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
obj-y += stm32/
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
obj-$(CONFIG_CRYPTO_DEV_TEGRA) += tegra/
+obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += ti/
obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
#obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig
new file mode 100644
index 000000000000..b5747c2ab8f8
--- /dev/null
+++ b/drivers/crypto/ti/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config CRYPTO_DEV_TI_MCRC64
+ tristate "Texas Instruments MCRC64 engine support"
+ depends on ARCH_K3 || COMPILE_TEST
+ select CRYPTO_HASH
+ select CRYPTO_CRC64_ISO3309
+ help
+ This enables support for the MCRC64 engine
+ which can be found on all AM62* and J722S devices.
+ MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
+ according to the ISO 3309 standard.
diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile
new file mode 100644
index 000000000000..94ffc2576137
--- /dev/null
+++ b/drivers/crypto/ti/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_CRYPTO_DEV_TI_MCRC64) += mcrc64.o
diff --git a/drivers/crypto/ti/mcrc64.c b/drivers/crypto/ti/mcrc64.c
new file mode 100644
index 000000000000..2be18ce81a27
--- /dev/null
+++ b/drivers/crypto/ti/mcrc64.c
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) Texas Instruments 2023 - http://www.ti.com
+ * Author: Kamlesh Gurudasani <kamlesh@ti.com>
+ */
+
+#include <linux/crc64.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <crypto/internal/hash.h>
+
+#include <asm/unaligned.h>
+
+#define DRIVER_NAME "mcrc64"
+#define CHKSUM_DIGEST_SIZE 8
+#define CHKSUM_BLOCK_SIZE 1
+
+/* Registers */
+#define CRC_CTRL0 0x0000 /* CRC Global Control Register 0 */
+#define CH_PSA_SWRE(ch) BIT(((ch) - 1) << 3) /* PSA Software Reset */
+
+#define CRC_CTRL1 0x0008 /* CRC Global Control Register 1 */
+#define PWDN BIT(0) /* Power Down */
+
+#define CRC_CTRL2 0x0010 /* CRC Global Control Register 2 */
+#define CH_MODE(ch, m) ((m) << (((ch) - 1) << 3))
+
+#define PSA_SIGREGL(ch) ((0x6 + (4 * ((ch) - 1))) << 4) /* Signature register */
+
+#define MCRC64_ALG_MASK 0x8000000000000000
+#define MCRC64_CRC64_POLY 0x000000000000001b
+
+#define MCRC64_AUTOSUSPEND_DELAY 50
+
+enum mcrc64_mode {
+ MCRC64_MODE_DATA_CAPTURE = 0,
+ MCRC64_MODE_AUTO,
+ MCRC64_MODE_SEMI_CPU,
+ MCRC64_MODE_FULL_CPU,
+ MCRC64_MODE_INVALID,
+};
+
+enum mcrc64_channel {
+ MCRC64_CHANNEL_1 = 1,
+ MCRC64_CHANNEL_2,
+ MCRC64_CHANNEL_3,
+ MCRC64_CHANNEL_4,
+ MCRC64_CHANNEL_INVALID,
+};
+
+struct mcrc64_data {
+ struct list_head list;
+ struct device *dev;
+ void __iomem *regs;
+};
+
+struct mcrc64_list {
+ struct list_head dev_list;
+ spinlock_t lock; /* protect dev_list */
+};
+
+static struct mcrc64_list mcrc64_dev_list = {
+ .dev_list = LIST_HEAD_INIT(mcrc64_dev_list.dev_list),
+ .lock = __SPIN_LOCK_UNLOCKED(mcrc64_dev_list.lock),
+};
+
+struct mcrc64_tfm_ctx {
+ struct mcrc64_data *dev_data;
+ u64 key;
+};
+
+struct mcrc64_desc_ctx {
+ u64 signature;
+};
+
+static struct mcrc64_data *mcrc64_get_dev(struct mcrc64_tfm_ctx *tctx)
+{
+ struct mcrc64_data *dev_data;
+
+ if (tctx->dev_data)
+ return tctx->dev_data;
+
+ spin_lock_bh(&mcrc64_dev_list.lock);
+ dev_data = list_first_entry(&mcrc64_dev_list.dev_list, struct mcrc64_data, list);
+ if (dev_data)
+ list_move_tail(&dev_data->list, &mcrc64_dev_list.dev_list);
+ spin_unlock_bh(&mcrc64_dev_list.lock);
+
+ return dev_data;
+}
+
+static int mcrc64_set_mode(void __iomem *regs, u32 channel, u32 mode)
+{
+ u32 mode_set_val;
+ u32 crc_ctrl2_reg = 0;
+
+ if (mode < 0 || mode >= MCRC64_MODE_INVALID)
+ return -EINVAL;
+
+ if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
+ return -EINVAL;
+
+ mode_set_val = crc_ctrl2_reg | CH_MODE(channel, mode);
+
+ /* Write CRC_CTRL2, set mode */
+ writel_relaxed(mode_set_val, regs + CRC_CTRL2);
+
+ return 0;
+}
+
+static int mcrc64_reset_signature(void __iomem *regs, u32 channel)
+{
+ u32 crc_ctrl0_reg, reset_val, reset_undo_val;
+
+ if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
+ return -EINVAL;
+
+ /* reset PSA */
+ crc_ctrl0_reg = readl_relaxed(regs + CRC_CTRL0);
+
+ reset_val = crc_ctrl0_reg | CH_PSA_SWRE(channel);
+ reset_undo_val = crc_ctrl0_reg & ~CH_PSA_SWRE(channel);
+
+ /* Write CRC_CTRL0 register, reset PSA register */
+ writel_relaxed(reset_val, regs + CRC_CTRL0);
+ writel_relaxed(reset_undo_val, regs + CRC_CTRL0);
+
+ return 0;
+}
+
+/* This helper implements crc64 calculation using CPU */
+static u64 mcrc64_calculate_sw_crc(u64 crc, u8 byte)
+{
+ u64 bit = 0;
+ u8 j;
+
+ for (j = 0; j < 8; j++) {
+ bit = crc & MCRC64_ALG_MASK;
+ crc <<= 1;
+ if (byte & (0x80 >> j))
+ bit ^= MCRC64_ALG_MASK;
+ if (bit)
+ crc ^= MCRC64_CRC64_POLY;
+ }
+
+ return crc;
+}
+
+static int mcrc64_calculate_crc(void __iomem *regs, u32 channel,
+ const u8 *d8, size_t length, u64 *crc64)
+{
+ void __iomem *psa_reg;
+ u64 signature = 0;
+
+ if (channel <= 0 || channel >= MCRC64_CHANNEL_INVALID)
+ return -EINVAL;
+
+ psa_reg = regs + PSA_SIGREGL(channel);
+
+ for (; length >= sizeof(u64); d8 += sizeof(u64), length -= sizeof(u64))
+ writeq_relaxed(cpu_to_be64p((u64 *)d8), psa_reg);
+
+ signature = readq_relaxed(psa_reg);
+
+ if (length) {
+ while (length--)
+ signature = mcrc64_calculate_sw_crc(signature, *d8++);
+
+ /* set capture mode */
+ int ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_DATA_CAPTURE);
+ if (ret)
+ return ret;
+
+ ret = mcrc64_reset_signature(regs, MCRC64_CHANNEL_1);
+ if (ret)
+ return ret;
+
+ writeq_relaxed(signature, psa_reg);
+
+ ret = mcrc64_set_mode(regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_FULL_CPU);
+ if (ret)
+ return ret;
+ }
+
+ *crc64 = signature;
+
+ return 0;
+}
+
+static int mcrc64_cra_init(struct crypto_tfm *tfm)
+{
+ struct mcrc64_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ struct mcrc64_data *dev_data;
+
+ dev_data = mcrc64_get_dev(tctx);
+ if (!dev_data)
+ return -ENODEV;
+
+ pm_runtime_get_sync(dev_data->dev);
+
+ tctx->key = 0;
+
+ return 0;
+}
+
+static void mcrc64_cra_exit(struct crypto_tfm *tfm)
+{
+ struct mcrc64_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
+ struct mcrc64_data *dev_data;
+
+ dev_data = mcrc64_get_dev(tctx);
+
+ pm_runtime_mark_last_busy(dev_data->dev);
+ pm_runtime_put_autosuspend(dev_data->dev);
+}
+
+static int mcrc64_setkey(struct crypto_shash *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct mcrc64_tfm_ctx *tctx = crypto_shash_ctx(tfm);
+
+ if (keylen != sizeof(u64))
+ return -EINVAL;
+
+ tctx->key = get_unaligned_le64(key);
+
+ return 0;
+}
+
+static int mcrc64_init(struct shash_desc *desc)
+{
+ struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
+ struct mcrc64_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+ struct mcrc64_data *dev_data;
+ void __iomem *psa_reg;
+
+ dev_data = mcrc64_get_dev(tctx);
+ if (!dev_data)
+ return -ENODEV;
+
+ pm_runtime_get_sync(dev_data->dev);
+
+ /* set capture mode */
+ int ret = mcrc64_set_mode(dev_data->regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_DATA_CAPTURE);
+ if (ret)
+ return ret;
+
+ /* reset PSA */
+ psa_reg = dev_data->regs + PSA_SIGREGL(MCRC64_CHANNEL_1);
+ ret = mcrc64_reset_signature(dev_data->regs, MCRC64_CHANNEL_1);
+ if (ret)
+ return ret;
+
+ /* write key */
+ writeq_relaxed(tctx->key, psa_reg);
+
+ /* set full cpu mode */
+ ret = mcrc64_set_mode(dev_data->regs, MCRC64_CHANNEL_1,
+ MCRC64_MODE_FULL_CPU);
+ if (ret)
+ return ret;
+
+ ctx->signature = readq_relaxed(psa_reg);
+
+ return 0;
+}
+
+static int mcrc64_update(struct shash_desc *desc, const u8 *d8,
+ unsigned int length)
+{
+ struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
+ struct mcrc64_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+ struct mcrc64_data *dev_data;
+
+ dev_data = mcrc64_get_dev(tctx);
+ if (!dev_data)
+ return -ENODEV;
+
+ return mcrc64_calculate_crc(dev_data->regs, MCRC64_CHANNEL_1,
+ d8, length, &ctx->signature);
+}
+
+static int mcrc64_final(struct shash_desc *desc, u8 *out)
+{
+ struct mcrc64_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ /* Send computed CRC */
+ put_unaligned_le64(ctx->signature, out);
+ return 0;
+}
+
+static int mcrc64_finup(struct shash_desc *desc, const u8 *data,
+ unsigned int length, u8 *out)
+{
+ return mcrc64_update(desc, data, length) ?:
+ mcrc64_final(desc, out);
+}
+
+static int mcrc64_digest(struct shash_desc *desc, const u8 *data,
+ unsigned int length, u8 *out)
+{
+ return mcrc64_init(desc) ?: mcrc64_finup(desc, data, length, out);
+}
+
+static unsigned int refcnt;
+static DEFINE_MUTEX(refcnt_lock);
+static struct shash_alg algs[] = {
+ /* CRC-64 */
+ {
+ .setkey = mcrc64_setkey,
+ .init = mcrc64_init,
+ .update = mcrc64_update,
+ .final = mcrc64_final,
+ .finup = mcrc64_finup,
+ .digest = mcrc64_digest,
+ .descsize = sizeof(struct mcrc64_desc_ctx),
+ .digestsize = CHKSUM_DIGEST_SIZE,
+ .base = {
+ .cra_name = CRC64_ISO3309_STRING,
+ .cra_driver_name = "mcrc64",
+ .cra_priority = 300,
+ .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
+ .cra_blocksize = CHKSUM_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct mcrc64_tfm_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_init = mcrc64_cra_init,
+ .cra_exit = mcrc64_cra_exit,
+ }
+ }
+};
+
+static int mcrc64_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mcrc64_data *dev_data;
+ int ret;
+
+ dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);
+ if (!dev_data)
+ return -ENOMEM;
+
+ dev_data->dev = dev;
+ dev_data->regs = devm_platform_ioremap_resource(pdev, 0);
+
+ platform_set_drvdata(pdev, dev_data);
+
+ spin_lock(&mcrc64_dev_list.lock);
+ list_add(&dev_data->list, &mcrc64_dev_list.dev_list);
+ spin_unlock(&mcrc64_dev_list.lock);
+
+ mutex_lock(&refcnt_lock);
+ if (!refcnt) {
+ ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
+ if (ret) {
+ mutex_unlock(&refcnt_lock);
+ dev_err(dev, "Failed to register\n");
+ return ret;
+ }
+ }
+ refcnt++;
+ mutex_unlock(&refcnt_lock);
+
+ pm_runtime_set_autosuspend_delay(dev, MCRC64_AUTOSUSPEND_DELAY);
+ pm_runtime_use_autosuspend(dev);
+
+ pm_runtime_get_noresume(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static int mcrc64_remove(struct platform_device *pdev)
+{
+ struct mcrc64_data *dev_data = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev_data->dev);
+ if (ret < 0)
+ return ret;
+
+ spin_lock(&mcrc64_dev_list.lock);
+ list_del(&dev_data->list);
+ spin_unlock(&mcrc64_dev_list.lock);
+
+ mutex_lock(&refcnt_lock);
+ if (!--refcnt)
+ crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
+ mutex_unlock(&refcnt_lock);
+
+ pm_runtime_disable(dev_data->dev);
+ pm_runtime_put_noidle(dev_data->dev);
+
+ return 0;
+}
+
+static int __maybe_unused mcrc64_suspend(struct device *dev)
+{
+ return pm_runtime_force_suspend(dev);
+}
+
+static int __maybe_unused mcrc64_resume(struct device *dev)
+{
+ return pm_runtime_force_resume(dev);
+}
+
+static const struct dev_pm_ops mcrc64_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mcrc64_suspend,
+ mcrc64_resume)
+};
+
+static const struct of_device_id of_match[] = {
+ { .compatible = "ti,am62-mcrc64", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_match);
+
+static struct platform_driver mcrc64_driver = {
+ .probe = mcrc64_probe,
+ .remove = mcrc64_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .pm = &mcrc64_pm_ops,
+ .of_match_table = of_match,
+ },
+};
+
+module_platform_driver(mcrc64_driver);
+
+MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh@ti.com>");
+MODULE_DESCRIPTION("Texas Instruments MCRC64 driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 4/6] crypto: ti - add driver for MCRC64 engine
2024-05-30 12:24 ` [PATCH v3 4/6] crypto: ti - add driver for MCRC64 engine kamlesh
@ 2024-06-11 12:02 ` Markus Elfring
0 siblings, 0 replies; 16+ messages in thread
From: Markus Elfring @ 2024-06-11 12:02 UTC (permalink / raw)
To: Kamlesh Gurudasani, devicetree, linux-crypto, linux-arm-kernel,
linux-stm32, Herbert Xu, Tero Kristo, Will Deacon
Cc: LKML, Andrew Morton, Alexandre Torgue, Catalin Marinas,
Conor Dooley, David S. Miller, Krzysztof Kozlowski,
Maxime Coquelin, Rob Herring, Vignesh Raghavendra
…
> +++ b/drivers/crypto/ti/mcrc64.c
…
> +static int mcrc64_probe(struct platform_device *pdev)
> +{
…
> + platform_set_drvdata(pdev, dev_data);
> +
> + spin_lock(&mcrc64_dev_list.lock);
> + list_add(&dev_data->list, &mcrc64_dev_list.dev_list);
> + spin_unlock(&mcrc64_dev_list.lock);
> +
> + mutex_lock(&refcnt_lock);
> + if (!refcnt) {
> + ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
…
> + }
> + refcnt++;
> + mutex_unlock(&refcnt_lock);
…
Would you become interested to apply lock guards?
https://elixir.bootlin.com/linux/v6.10-rc2/source/include/linux/cleanup.h#L124
Regards,
Markus
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 5/6 DONOTMERGE] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
` (3 preceding siblings ...)
2024-05-30 12:24 ` [PATCH v3 4/6] crypto: ti - add driver for MCRC64 engine kamlesh
@ 2024-05-30 12:24 ` kamlesh
2024-05-30 12:24 ` [PATCH v3 6/6 DONOTMERGE] arm64: defconfig: enable TI MCRC64 module kamlesh
2024-06-10 14:33 ` [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode Kamlesh Gurudasani
6 siblings, 0 replies; 16+ messages in thread
From: kamlesh @ 2024-05-30 12:24 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree, Kamlesh Gurudasani
From: Kamlesh Gurudasani <kamlesh@ti.com>
Add the address space for MCRC64 to the ranges property of the
cbass_main node and add dt node for MCRC64 engine
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 7 +++++++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index e9cffca073ef..f80fd753382b 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -216,6 +216,13 @@ crypto: crypto@40900000 {
dma-names = "tx", "rx1", "rx2";
};
+ crc: crc@30300000 {
+ compatible = "ti,am62-mcrc64";
+ reg = <0x00 0x30300000 0x00 0x1000>;
+ clocks = <&k3_clks 116 0>;
+ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+ };
+
secure_proxy_sa3: mailbox@43600000 {
bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi
index f0781f2bea29..edb2cb592ee1 100644
--- a/arch/arm64/boot/dts/ti/k3-am62.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi
@@ -66,6 +66,7 @@ cbass_main: bus@f0000 {
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+ <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC64 */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 6/6 DONOTMERGE] arm64: defconfig: enable TI MCRC64 module
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
` (4 preceding siblings ...)
2024-05-30 12:24 ` [PATCH v3 5/6 DONOTMERGE] arm64: dts: ti: k3-am62: Add dt node, cbass_main ranges for MCRC64 kamlesh
@ 2024-05-30 12:24 ` kamlesh
2024-06-10 14:33 ` [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode Kamlesh Gurudasani
6 siblings, 0 replies; 16+ messages in thread
From: kamlesh @ 2024-05-30 12:24 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree, Kamlesh Gurudasani
From: Kamlesh Gurudasani <kamlesh@ti.com>
J722S and all AM62** devices include MCRC64 engine for crc64 calculation.
Enable module to be built for them.
Also enable algif_hash module, which is needed to access MCRC64 module
from userspace.
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2c30d617e180..aaeee392df10 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1630,6 +1630,7 @@ CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_GHASH_ARM64_CE=y
@@ -1653,6 +1654,7 @@ CONFIG_CRYPTO_DEV_HISI_ZIP=m
CONFIG_CRYPTO_DEV_HISI_HPRE=m
CONFIG_CRYPTO_DEV_HISI_TRNG=m
CONFIG_CRYPTO_DEV_SA2UL=m
+CONFIG_CRYPTO_DEV_TI_MCRC64=m
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
2024-05-30 12:24 [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode kamlesh
` (5 preceding siblings ...)
2024-05-30 12:24 ` [PATCH v3 6/6 DONOTMERGE] arm64: defconfig: enable TI MCRC64 module kamlesh
@ 2024-06-10 14:33 ` Kamlesh Gurudasani
2024-06-11 2:31 ` Herbert Xu
6 siblings, 1 reply; 16+ messages in thread
From: Kamlesh Gurudasani @ 2024-06-10 14:33 UTC (permalink / raw)
To: herbert, kristo, will
Cc: akpm, davem, mcoquelin.stm32, alexandre.torgue, robh,
krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree
<kamlesh@ti.com> writes:
> From: Kamlesh Gurudasani <kamlesh@ti.com>
>
> MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> according to the ISO 3309 standard.
>
Hi Herbert,
Could you please review this and let me know if any changes are needed
to get it merged.
Thanks,
Kamlesh
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
2024-06-10 14:33 ` [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode Kamlesh Gurudasani
@ 2024-06-11 2:31 ` Herbert Xu
2024-06-11 3:13 ` Eric Biggers
0 siblings, 1 reply; 16+ messages in thread
From: Herbert Xu @ 2024-06-11 2:31 UTC (permalink / raw)
To: Kamlesh Gurudasani, Eric Biggers
Cc: kristo, will, akpm, davem, mcoquelin.stm32, alexandre.torgue,
robh, krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree
On Mon, Jun 10, 2024 at 08:03:44PM +0530, Kamlesh Gurudasani wrote:
> <kamlesh@ti.com> writes:
>
> > From: Kamlesh Gurudasani <kamlesh@ti.com>
> >
> > MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> > according to the ISO 3309 standard.
>
> Could you please review this and let me know if any changes are needed
> to get it merged.
Eric Biggers had concerns about adding this to the kernel. I'd
like know if he's OK with this or not.
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
2024-06-11 2:31 ` Herbert Xu
@ 2024-06-11 3:13 ` Eric Biggers
2024-06-11 3:17 ` Herbert Xu
0 siblings, 1 reply; 16+ messages in thread
From: Eric Biggers @ 2024-06-11 3:13 UTC (permalink / raw)
To: Herbert Xu
Cc: Kamlesh Gurudasani, kristo, will, akpm, davem, mcoquelin.stm32,
alexandre.torgue, robh, krzysztof.kozlowski+dt, conor+dt,
vigneshr, catalin.marinas, linux-kernel, linux-crypto,
linux-stm32, linux-arm-kernel, devicetree
On Tue, Jun 11, 2024 at 10:31:45AM +0800, Herbert Xu wrote:
> On Mon, Jun 10, 2024 at 08:03:44PM +0530, Kamlesh Gurudasani wrote:
> > <kamlesh@ti.com> writes:
> >
> > > From: Kamlesh Gurudasani <kamlesh@ti.com>
> > >
> > > MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC)
> > > according to the ISO 3309 standard.
> >
> > Could you please review this and let me know if any changes are needed
> > to get it merged.
>
> Eric Biggers had concerns about adding this to the kernel. I'd
> like know if he's OK with this or not.
>
I thought the rule is that there needs to be an in-kernel user to add algorithms
to the crypto API? Is there any precedent for adding new algorithms purely so
that accelerators that implement them can be accessed from userspace via AF_ALG?
Even if acceptable, the motivation for this one does seem weak, given that a
userspace software implementation would actually be faster. It could be
marginally useful for freeing up the CPU for other tasks if the inputs being
processed are very large (probably at least several megabytes), though.
- Eric
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
2024-06-11 3:13 ` Eric Biggers
@ 2024-06-11 3:17 ` Herbert Xu
2024-09-06 11:14 ` Kamlesh Gurudasani
0 siblings, 1 reply; 16+ messages in thread
From: Herbert Xu @ 2024-06-11 3:17 UTC (permalink / raw)
To: Eric Biggers
Cc: Kamlesh Gurudasani, kristo, will, akpm, davem, mcoquelin.stm32,
alexandre.torgue, robh, krzysztof.kozlowski+dt, conor+dt,
vigneshr, catalin.marinas, linux-kernel, linux-crypto,
linux-stm32, linux-arm-kernel, devicetree
On Mon, Jun 10, 2024 at 08:13:14PM -0700, Eric Biggers wrote:
>
> I thought the rule is that there needs to be an in-kernel user to add algorithms
> to the crypto API? Is there any precedent for adding new algorithms purely so
> that accelerators that implement them can be accessed from userspace via AF_ALG?
I agree. Perhaps this driver could instead be added as a simple
char device that is then used directly by the intended user without
going through the Crypto API at all.
That would make it a lot simpler.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
2024-06-11 3:17 ` Herbert Xu
@ 2024-09-06 11:14 ` Kamlesh Gurudasani
2024-09-13 10:35 ` Herbert Xu
0 siblings, 1 reply; 16+ messages in thread
From: Kamlesh Gurudasani @ 2024-09-06 11:14 UTC (permalink / raw)
To: Herbert Xu, Eric Biggers
Cc: kristo, will, akpm, davem, mcoquelin.stm32, alexandre.torgue,
robh, krzysztof.kozlowski+dt, conor+dt, vigneshr, catalin.marinas,
linux-kernel, linux-crypto, linux-stm32, linux-arm-kernel,
devicetree
Herbert Xu <herbert@gondor.apana.org.au> writes:
> On Mon, Jun 10, 2024 at 08:13:14PM -0700, Eric Biggers wrote:
>>
>> I thought the rule is that there needs to be an in-kernel user to add algorithms
>> to the crypto API? Is there any precedent for adding new algorithms purely so
>> that accelerators that implement them can be accessed from userspace via AF_ALG?
>
> I agree. Perhaps this driver could instead be added as a simple
> char device that is then used directly by the intended user without
> going through the Crypto API at all.
>
> That would make it a lot simpler.
Thanks for all the support Herbert, Eric.
Just wanted to confirm, if this is being rejected primarily because
1. there is no in-kernel user for crc64-iso3309
2. or poor performance benefit of using it from userspace
The context for asking is that we have another superset IP known as MCRC
(this one is MCRC64), which supports crc8/16/32/64(iso-3309).
That IP has working DMA and will give good offloading numbers.
We are planning to send drivers for crc8/16/32 for MCRC
1.should I put efforts for crc64-iso3309 as well or
2.drop the crc64-iso3309 and send only for remaining
crc8/16/32(standard algorithms with already in-kernel user).
All our devices either have MCRC or MCRC64.
Thanks,
Kamlesh
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/6] Add support for MCRC64 engine to calculate 64-bit CRC in Full-CPU mode
2024-09-06 11:14 ` Kamlesh Gurudasani
@ 2024-09-13 10:35 ` Herbert Xu
0 siblings, 0 replies; 16+ messages in thread
From: Herbert Xu @ 2024-09-13 10:35 UTC (permalink / raw)
To: Kamlesh Gurudasani
Cc: Eric Biggers, kristo, will, akpm, davem, mcoquelin.stm32,
alexandre.torgue, robh, krzysztof.kozlowski+dt, conor+dt,
vigneshr, catalin.marinas, linux-kernel, linux-crypto,
linux-stm32, linux-arm-kernel, devicetree
On Fri, Sep 06, 2024 at 04:44:44PM +0530, Kamlesh Gurudasani wrote:
>
> Just wanted to confirm, if this is being rejected primarily because
> 1. there is no in-kernel user for crc64-iso3309
> 2. or poor performance benefit of using it from userspace
Essentially we don't want to add every random algorithm to the crypto
API because we may end up having to maintain them long after the users
have disappeared.
For a special-purpose algorithm like this, it's perfectly fine to have
a custom driver to be made so that your user-space app can access the
hardware.
> The context for asking is that we have another superset IP known as MCRC
> (this one is MCRC64), which supports crc8/16/32/64(iso-3309).
>
> That IP has working DMA and will give good offloading numbers.
>
> We are planning to send drivers for crc8/16/32 for MCRC
> 1.should I put efforts for crc64-iso3309 as well or
> 2.drop the crc64-iso3309 and send only for remaining
> crc8/16/32(standard algorithms with already in-kernel user).
>
> All our devices either have MCRC or MCRC64.
Do any existing kernel users benefit sufficiently from these algorithms
being offloaded? If no then there is no need to bother.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply [flat|nested] 16+ messages in thread