Re: [PATCH 0/9] Add CPU-type to topology

Ricardo Neri
2024-06-27T12:45:49Z

On Thu, Jun 20, 2024 at 08:06:11AM -0700, Dave Hansen wrote:
> On 6/19/24 14:25, Brice Goglin wrote:
> > Good point. From this patch series, I understand that the current kernel
> > side doesn't care about these different E-cores. However it might be
> > good to expose them as different cpu-types (or better name) to userspace ?
> >
> > Something like type 0 = P-core, 1 = normal E-core, 2 = low power E-core ?
>
> The first priority here is getting the kernel to comprehend these types
> for architectural purposes: when there are functional differences
> between the cores.
>
> Let's get that in place, first. Then we can discuss the possibility of
> new ABI in the area.
>
> Did the ARM folks ever do a sysfs ABI for big.LITTLE? I don't see
> anything obvious in Documentation/ABI/testing/sysfs-devices-system-cpu.
>

ARM has the interface /sys/devices/system/cpu/cpu0/regs/identification

Here they show the Main ID Register [A]. This register has CPU
identification fields such as architecture and other details. The
architecture can be specified as a number or refer to architecture-specific
features in other registers.

On my DragonBoard 845c, this interface shows different values for different
types of CPUs.

For functionality, there is also a /sys/devices/system/cpu/aarch32_el0. It
lists the CPUs that can 32-bit ARM programs on processors in which only a
subset of CPUs can do it.

ARM gives userspace specific details. This makes more sense to me. Instead
of reading these details, user space would have to infer these details if
a CPU type was given in sysfs.

Having said that, Intel does have a CPUID leaf that gives the CPU type. Such
leaf also has a "Native Model ID". Exposing only the CPU type may not be
sufficient.

[A]. https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/MIDR-EL1--Main-ID-Register