From: Rob Clark <robdclark@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
Rob Clark <robdclark@chromium.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info
Date: Mon, 17 Jun 2024 15:51:14 -0700 [thread overview]
Message-ID: <20240617225127.23476-5-robdclark@gmail.com> (raw)
In-Reply-To: <20240617225127.23476-1-robdclark@gmail.com>
From: Rob Clark <robdclark@chromium.org>
Introduce a6xx_info where we can stash gen specific stuff without
polluting the toplevel adreno_info struct.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 65 +++++++++++++++++------
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++-
4 files changed, 67 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index bcc2f4d8cfc6..96d93251fdd6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -7,6 +7,7 @@
*/
#include "adreno_gpu.h"
+#include "a6xx_gpu.h"
#include "a6xx.xml.h"
#include "a6xx_gmu.xml.h"
@@ -465,7 +466,9 @@ static const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a610_zap.mdt",
- .hwcg = a612_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a612_hwcg,
+ },
/*
* There are (at least) three SoCs implementing A610: SM6125
* (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
@@ -493,7 +496,9 @@ static const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mbn",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 128, 1 },
@@ -513,6 +518,8 @@ static const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
+ .a6xx = &(struct a6xx_info) {
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 169, 1 },
@@ -531,7 +538,9 @@ static const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 138, 1 },
@@ -550,7 +559,9 @@ static const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 190, 1 },
@@ -569,7 +580,9 @@ static const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 120, 4 },
@@ -593,7 +606,9 @@ static const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a630_zap.mdt",
- .hwcg = a630_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a630_hwcg,
+ },
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
.family = ADRENO_6XX_GEN2,
@@ -607,7 +622,9 @@ static const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a640_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 1, 1 },
@@ -626,7 +643,9 @@ static const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a650_zap.mdt",
- .hwcg = a650_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a650_hwcg,
+ },
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -648,7 +667,9 @@ static const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mdt",
- .hwcg = a660_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a660_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06030500),
@@ -663,7 +684,9 @@ static const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mbn",
- .hwcg = a660_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a660_hwcg,
+ },
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -684,7 +707,9 @@ static const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a640_hwcg,
+ },
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06090000),
.family = ADRENO_6XX_GEN4,
@@ -698,7 +723,9 @@ static const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a690_zap.mdt",
- .hwcg = a690_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a690_hwcg,
+ },
.address_space_size = SZ_16G,
}
};
@@ -901,7 +928,9 @@ static const struct adreno_info a7xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a702_zap.mbn",
- .hwcg = a702_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a702_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 236, 1 },
@@ -921,7 +950,9 @@ static const struct adreno_info a7xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a730_zap.mdt",
- .hwcg = a730_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a730_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
@@ -936,7 +967,9 @@ static const struct adreno_info a7xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a740_zap.mdt",
- .hwcg = a740_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a740_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
@@ -951,6 +984,8 @@ static const struct adreno_info a7xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "gen70900_zap.mbn",
+ .a6xx = &(struct a6xx_info) {
+ },
.address_space_size = SZ_16G,
}
};
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index eea64ec1bfaa..7e01fb551f12 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
unsigned int i;
u32 val, clock_cntl_on, cgc_mode;
- if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu)))
+ if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
return;
if (adreno_is_a630(adreno_gpu))
@@ -426,7 +426,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
state ? 0x5555 : 0);
}
- if (!adreno_gpu->info->hwcg) {
+ if (!adreno_gpu->info->a6xx->hwcg) {
gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0);
@@ -455,7 +455,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
- for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
+ for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++)
gpu_write(gpu, reg->offset, state ? reg->value : 0);
/* Enable SP clock */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 0463a2006822..61c51e9c7f06 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -12,6 +12,15 @@
extern bool hang_debug;
+/**
+ * struct a6xx_info - a6xx specific information from device table
+ *
+ * @hwcg: hw clock gating register sequence
+ */
+struct a6xx_info {
+ const struct adreno_reglist *hwcg;
+};
+
struct a6xx_gpu {
struct adreno_gpu base;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 695e00ae1f62..13e68222228f 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -82,6 +82,8 @@ struct adreno_speedbin {
uint16_t speedbin;
};
+struct a6xx_info;
+
struct adreno_info {
const char *machine;
/**
@@ -98,7 +100,9 @@ struct adreno_info {
struct msm_gpu *(*init)(struct drm_device *dev);
const char *zapfw;
u32 inactive_period;
- const struct adreno_reglist *hwcg;
+ union {
+ const struct a6xx_info *a6xx;
+ };
u64 address_space_size;
/**
* @speedbins: Optional table of fuse to speedbin mappings
--
2.45.2
next prev parent reply other threads:[~2024-06-17 22:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-17 22:51 [PATCH v3 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
2024-06-17 22:51 ` [PATCH v3 1/5] drm/msm/adreno: Split up giant device table Rob Clark
2024-06-17 23:09 ` Dmitry Baryshkov
2024-06-18 11:08 ` Konrad Dybcio
2024-06-17 22:51 ` [PATCH v3 2/5] drm/msm/adreno: Split catalog into separate files Rob Clark
2024-06-17 23:10 ` Dmitry Baryshkov
2024-06-18 11:10 ` Konrad Dybcio
2024-06-17 22:51 ` [PATCH v3 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog Rob Clark
2024-06-17 23:10 ` Dmitry Baryshkov
2024-06-18 11:11 ` Konrad Dybcio
2024-06-17 22:51 ` Rob Clark [this message]
2024-06-18 8:30 ` [PATCH v3 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Dmitry Baryshkov
2024-06-18 16:33 ` Rob Clark
2024-06-18 17:26 ` Dmitry Baryshkov
2024-06-18 11:13 ` Konrad Dybcio
2024-06-17 22:51 ` [PATCH v3 5/5] drm/msm/adreno: Move CP_PROTECT settings to hw catalog Rob Clark
2024-06-18 8:28 ` Dmitry Baryshkov
2024-06-18 11:17 ` Konrad Dybcio
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