Re: [RESEND PATCH 05/12] perf/x86: Add config_mask to represent EVENTSEL bitmask

Peter Zijlstra
2024-06-24T08:28:18Z

On Fri, Jun 21, 2024 at 02:34:35PM -0400, Liang, Kan wrote:
>
>
> On 2024-06-20 12:16 p.m., Liang, Kan wrote:
> >
> >
> > On 2024-06-20 3:44 a.m., Peter Zijlstra wrote:
> >> On Tue, Jun 18, 2024 at 08:10:37AM -0700, kan.liang@linux.intel.com wrote:
> >>> From: Kan Liang <kan.liang@linux.intel.com>
> >>>
> >>> Different vendors may support different fields in EVENTSEL MSR, such as
> >>> Intel would introduce new fields umask2 and eq bits in EVENTSEL MSR
> >>> since Perfmon version 6. However, a fixed mask X86_RAW_EVENT_MASK is
> >>> used to filter the attr.config.
> >>>
> >>
> >>> @@ -1231,6 +1233,11 @@ static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
> >>> return hweight64(hybrid(pmu, fixed_cntr_mask64));
> >>> }
> >>>
> >>> +static inline u64 x86_pmu_get_event_config(struct perf_event *event)
> >>> +{
> >>> + return event->attr.config & hybrid(event->pmu, config_mask);
> >>> +}
> >>
> >> Seriously, we're going to be having such major event encoding
> >> differences between cores on a single chip?
> >
> > For LNL, no. But ARL-H may have an event encoding differences.
> > I will double check.
>
> There are two generations of e-core on ARL-H. The event encoding is
> different.
>
> The new fields umask2 and eq bits are enumerated by CPUID.(EAX=23H,
> ECX=0H):EBX. They are supported by CPU 11 but not CPU 12.
>
> CPU 11:
> 0x00000023 0x00: eax=0x0000000f ebx=0x00000003 ecx=0x00000008
> edx=0x00000000
> CPU 12:
> 0x00000023 0x00: eax=0x0000000b ebx=0x00000000 ecx=0x00000006
> edx=0x00000000
>

*groan*...

So we're going to be having 3 PMUs on that thing I suppose. Oh well.