Re: [RESEND PATCH 07/12] perf/x86/intel: Support Perfmon MSRs aliasing

Peter Zijlstra
2024-06-20T08:02:34Z

On Tue, Jun 18, 2024 at 08:10:39AM -0700, kan.liang@linux.intel.com wrote:
> @@ -6179,6 +6181,11 @@ static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
> }
> }
>
> +static inline int intel_pmu_addr_offset(int index, bool eventsel)
> +{
> + return MSR_IA32_PMC_STEP * index;
> +}

This should have v6 in the name or somesuch... no?

> static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
> { hybrid_small, "cpu_atom" },
> { hybrid_big, "cpu_core" },
> @@ -7153,6 +7160,14 @@ __init int intel_pmu_init(void)
> pr_cont("full-width counters, ");
> }
>
> + /* Support V6+ MSR Aliasing */
> + if (x86_pmu.version >= 6) {
> + x86_pmu.perfctr = MSR_IA32_PMC_GP0_CTR;
> + x86_pmu.eventsel = MSR_IA32_PMC_GP0_CFG_A;
> + x86_pmu.fixedctr = MSR_IA32_PMC_FX0_CTR;
> + x86_pmu.addr_offset = intel_pmu_addr_offset;
> + }