Re: [RESEND PATCH 02/12] perf/x86: Support counter mask

Liang, Kan
2024-06-20T16:02:55Z

On 2024-06-20 3:06 a.m., Peter Zijlstra wrote:
> On Tue, Jun 18, 2024 at 08:10:34AM -0700, kan.liang@linux.intel.com wrote:
>
>> + for_each_set_bit(idx, c->idxmsk, x86_pmu_num_counters(NULL)) {
>> if (new == -1 || hwc->idx == idx)
>> /* assign free slot, prefer hwc->idx */
>> old = cmpxchg(nb->owners + idx, NULL, event);
>
>> +static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
>> +{
>> + return hweight64(hybrid(pmu, fixed_cntr_mask64));
>> +}
>
>
> This is wrong. You don't iterate a bitmask by the number of bits set,
> but by the highest set bit in the mask.

It seems we need two functions for the number.
For the above iterate case, yes, we need the highest set bit to tell the
possible max number.

There could be other cases as below. An exact number of available
counters are required.

-void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
- u64 intel_ctrl)
+void x86_pmu_show_pmu_cap(struct pmu *pmu)
{
pr_info("... version: %d\n", x86_pmu.version);
pr_info("... bit width: %d\n",
x86_pmu.cntval_bits);
- pr_info("... generic registers: %d\n", num_counters);
+ pr_info("... generic registers: %d\n",
x86_pmu_num_counters(pmu));
I will add two functions, x86_pmu_max_num_counters() and
x86_pmu_num_counters().

Thanks,
Kan