From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: mingo@kernel.org, acme@kernel.org, namhyung@kernel.org,
irogers@google.com, adrian.hunter@intel.com,
alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org,
ak@linux.intel.com, eranian@google.com,
Sandipan Das <sandipan.das@amd.com>,
Ravi Bangoria <ravi.bangoria@amd.com>,
silviazhao <silviazhao-oc@zhaoxin.com>,
CodyYao-oc <CodyYao-oc@zhaoxin.com>
Subject: Re: [RESEND PATCH 02/12] perf/x86: Support counter mask
Date: Thu, 20 Jun 2024 09:06:49 +0200 [thread overview]
Message-ID: <20240620070649.GQ31592@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20240618151044.1318612-3-kan.liang@linux.intel.com>
On Tue, Jun 18, 2024 at 08:10:34AM -0700, kan.liang@linux.intel.com wrote:
> + for_each_set_bit(idx, c->idxmsk, x86_pmu_num_counters(NULL)) {
> if (new == -1 || hwc->idx == idx)
> /* assign free slot, prefer hwc->idx */
> old = cmpxchg(nb->owners + idx, NULL, event);
> +static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
> +{
> + return hweight64(hybrid(pmu, fixed_cntr_mask64));
> +}
This is wrong. You don't iterate a bitmask by the number of bits set,
but by the highest set bit in the mask.
next prev parent reply other threads:[~2024-06-20 7:07 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-18 15:10 [RESEND PATCH 00/12] Support Lunar Lake and Arrow Lake core PMU kan.liang
2024-06-18 15:10 ` [RESEND PATCH 01/12] perf/x86/intel: Support the PEBS event mask kan.liang
2024-06-20 7:02 ` Peter Zijlstra
2024-06-20 15:58 ` Liang, Kan
2024-06-21 14:19 ` Liang, Kan
2024-06-24 8:29 ` Peter Zijlstra
2024-06-24 8:21 ` Peter Zijlstra
2024-06-18 15:10 ` [RESEND PATCH 02/12] perf/x86: Support counter mask kan.liang
2024-06-20 7:06 ` Peter Zijlstra [this message]
2024-06-20 16:02 ` Liang, Kan
2024-06-18 15:10 ` [RESEND PATCH 03/12] perf/x86: Add Lunar Lake and Arrow Lake support kan.liang
2024-06-18 15:10 ` [RESEND PATCH 04/12] perf/x86/intel: Support new data source for Lunar Lake kan.liang
2024-06-20 7:34 ` Peter Zijlstra
2024-06-20 16:09 ` Liang, Kan
2024-06-18 15:10 ` [RESEND PATCH 05/12] perf/x86: Add config_mask to represent EVENTSEL bitmask kan.liang
2024-06-20 7:44 ` Peter Zijlstra
2024-06-20 16:16 ` Liang, Kan
2024-06-21 18:34 ` Liang, Kan
2024-06-24 8:28 ` Peter Zijlstra
2024-06-24 15:36 ` Liang, Kan
2024-06-24 8:26 ` Peter Zijlstra
2024-06-18 15:10 ` [RESEND PATCH 06/12] perf/x86/intel: Support PERFEVTSEL extension kan.liang
2024-06-18 15:10 ` [RESEND PATCH 07/12] perf/x86/intel: Support Perfmon MSRs aliasing kan.liang
2024-06-20 8:02 ` Peter Zijlstra
2024-06-20 16:17 ` Liang, Kan
2024-06-18 15:10 ` [RESEND PATCH 08/12] perf/x86: Extend event update interface kan.liang
2024-06-20 8:38 ` Peter Zijlstra
2024-06-20 16:18 ` Liang, Kan
2024-06-18 15:10 ` [RESEND PATCH 09/12] perf: Extend perf_output_read kan.liang
2024-06-20 9:00 ` Peter Zijlstra
2024-06-20 10:01 ` Peter Zijlstra
2024-06-18 15:10 ` [RESEND PATCH 10/12] perf/x86/intel: Move PEBS event update after the sample output kan.liang
2024-06-18 15:10 ` [RESEND PATCH 11/12] perf/x86/intel: Support PEBS counters snapshotting kan.liang
2024-06-18 15:10 ` [RESEND PATCH 12/12] perf/x86/intel: Support RDPMC metrics clear mode kan.liang
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