Re: [RESEND PATCH 05/12] perf/x86: Add config_mask to represent EVENTSEL bitmask

[Peter Zijlstra <peterz@infradead.org>]

On Tue, Jun 18, 2024 at 08:10:37AM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> Different vendors may support different fields in EVENTSEL MSR, such as
> Intel would introduce new fields umask2 and eq bits in EVENTSEL MSR
> since Perfmon version 6. However, a fixed mask X86_RAW_EVENT_MASK is
> used to filter the attr.config.
> 

> @@ -1231,6 +1233,11 @@ static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
>  	return hweight64(hybrid(pmu, fixed_cntr_mask64));
>  }
>  
> +static inline u64 x86_pmu_get_event_config(struct perf_event *event)
> +{
> +	return event->attr.config & hybrid(event->pmu, config_mask);
> +}

Seriously, we're going to be having such major event encoding
differences between cores on a single chip?