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Peter Anvin" , linux-kernel@vger.kernel.org, jacob.jun.pan@linux.intel.com Subject: Re: [PATCH v2] x86/irq: Fix comment on IRQ vector layout Message-ID: <20240627152708.3abda399@jacob-builder> In-Reply-To: <20240626194324.110388-1-sohil.mehta@intel.com> References: <20240626194324.110388-1-sohil.mehta@intel.com> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 26 Jun 2024 19:43:24 +0000, Sohil Mehta wrote: > commit f5a3562ec9dd ("x86/irq: Reserve a per CPU IDT vector for posted > MSIs") changed the first system vector from LOCAL_TIMER_VECTOR to > POSTED_MSI_NOTIFICATION_VECTOR. Reflect this change in the vector layout > comment as well. > > However, instead of pointing to the specific vector, use the > FIRST_SYSTEM_VECTOR indirection which essentially refers to the same. > This would avoid unnecessary modifications to the same comment whenever > additional system vectors get added. > > Signed-off-by: Sohil Mehta > --- > v2: Update the table to denote the other device interrupts range. [Jacob > Pan] > > v1: > https://lore.kernel.org/lkml/20240618201320.2066726-1-sohil.mehta@intel.com/ > > arch/x86/include/asm/irq_vectors.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/include/asm/irq_vectors.h > b/arch/x86/include/asm/irq_vectors.h index 13aea8fc3d45..47051871b436 > 100644 --- a/arch/x86/include/asm/irq_vectors.h > +++ b/arch/x86/include/asm/irq_vectors.h > @@ -18,8 +18,8 @@ > * Vectors 0 ... 31 : system traps and exceptions - hardcoded events > * Vectors 32 ... 127 : device interrupts > * Vector 128 : legacy int80 syscall interface > - * Vectors 129 ... LOCAL_TIMER_VECTOR-1 > - * Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts > + * Vectors 129 ... FIRST_SYSTEM_VECTOR-1 : device interrupts > + * Vectors FIRST_SYSTEM_VECTOR ... 255 : special interrupts > * > * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. > * Reviewed-by: Jacob Pan Thanks, Jacob