From: Sean Anderson <sean.anderson@linux.dev>
To: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
linux-phy@lists.infradead.org
Cc: Vinod Koul <vkoul@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-kernel@vger.kernel.org, Michal Simek <michal.simek@amd.com>,
Sean Anderson <sean.anderson@linux.dev>
Subject: [PATCH v3 3/5] phy: zynqmp: Only wait for PLL lock "primary" instances
Date: Fri, 28 Jun 2024 16:55:38 -0400 [thread overview]
Message-ID: <20240628205540.3098010-4-sean.anderson@linux.dev> (raw)
In-Reply-To: <20240628205540.3098010-1-sean.anderson@linux.dev>
For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.
The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
(no changes since v2)
Changes in v2:
- Move the logic for waiting on PLL lock to xpsgtr_wait_pll_lock
drivers/phy/xilinx/phy-zynqmp.c | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqmp.c
index a1cf32024efb..4d697e11d8eb 100644
--- a/drivers/phy/xilinx/phy-zynqmp.c
+++ b/drivers/phy/xilinx/phy-zynqmp.c
@@ -294,10 +294,30 @@ static int xpsgtr_wait_pll_lock(struct phy *phy)
struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
unsigned int timeout = TIMEOUT_US;
+ u8 protocol = gtr_phy->protocol;
int ret;
dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
+ /*
+ * For DP and PCIe, only the instance 0 PLL is used. Switch to that phy
+ * so we wait on the right PLL.
+ */
+ if ((protocol == ICM_PROTOCOL_DP || protocol == ICM_PROTOCOL_PCIE) &&
+ gtr_phy->instance) {
+ int i;
+
+ for (i = 0; i < NUM_LANES; i++) {
+ gtr_phy = >r_dev->phys[i];
+
+ if (gtr_phy->protocol == protocol && !gtr_phy->instance)
+ goto got_phy;
+ }
+
+ return -EBUSY;
+ }
+
+got_phy:
while (1) {
u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
@@ -625,15 +645,7 @@ static int xpsgtr_phy_power_on(struct phy *phy)
/* Skip initialization if not required. */
if (!xpsgtr_phy_init_required(gtr_phy))
return ret;
- /*
- * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
- * cumulating waits for both lanes. The user is expected to initialize
- * lane 0 last.
- */
- if (gtr_phy->protocol != ICM_PROTOCOL_DP || !gtr_phy->instance)
- ret = xpsgtr_wait_pll_lock(phy);
-
- return ret;
+ return xpsgtr_wait_pll_lock(phy);
}
static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
--
2.35.1.1320.gc452695387.dirty
next prev parent reply other threads:[~2024-06-28 20:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-28 20:55 [PATCH v3 0/5] phy: zynqmp: Fixes and debugfs support Sean Anderson
2024-06-28 20:55 ` [PATCH v3 1/5] phy: zynqmp: Enable reference clock correctly Sean Anderson
2024-06-28 20:55 ` [PATCH v3 2/5] phy: zynqmp: Store instance instead of type Sean Anderson
2024-06-28 20:55 ` Sean Anderson [this message]
2024-06-28 20:55 ` [PATCH v3 4/5] phy: zynqmp: Take the phy mutex in xlate Sean Anderson
2024-06-28 20:55 ` [PATCH v3 5/5] phy: zynqmp: Add debugfs support Sean Anderson
2024-07-02 13:35 ` [PATCH v3 0/5] phy: zynqmp: Fixes and " Vinod Koul
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