From: Xu Lu <luxu.kernel@bytedance.com>
To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, paul.walmsley@sifive.com
Cc: palmer@dabbelt.com, aou@eecs.berkeley.edu,
apatel@ventanamicro.com, sunilvl@ventanamicro.com,
iommu@lists.linux.dev, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux@rivosinc.com,
baolu.lu@linux.intel.com, lihangjing@bytedance.com,
xieyongji@bytedance.com, Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH 1/1] iommu/riscv: Support sharing irq lines between iommu queues
Date: Mon, 1 Jul 2024 15:29:08 +0800 [thread overview]
Message-ID: <20240701072908.25503-2-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20240701072908.25503-1-luxu.kernel@bytedance.com>
When the number of wired interrupt lines is less than the number of
iommu queues, we should assign one irq line for several queues and
configure csr icvec accordingly.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
drivers/iommu/riscv/iommu-platform.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/iommu/riscv/iommu-platform.c b/drivers/iommu/riscv/iommu-platform.c
index da336863f152..1d0af1260d5b 100644
--- a/drivers/iommu/riscv/iommu-platform.c
+++ b/drivers/iommu/riscv/iommu-platform.c
@@ -60,6 +60,10 @@ static int riscv_iommu_platform_probe(struct platform_device *pdev)
for (vec = 0; vec < iommu->irqs_count; vec++)
iommu->irqs[vec] = platform_get_irq(pdev, vec);
+ for (vec = iommu->irqs_count; vec < RISCV_IOMMU_INTR_COUNT; vec++)
+ iommu->irqs[vec] = platform_get_irq(pdev,
+ (vec % iommu->irqs_count));
+
/* Enable wire-signaled interrupts, fctl.WSI */
if (!(iommu->fctl & RISCV_IOMMU_FCTL_WSI)) {
iommu->fctl |= RISCV_IOMMU_FCTL_WSI;
--
2.20.1
next prev parent reply other threads:[~2024-07-01 7:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-01 7:29 [PATCH 0/1] iommu/riscv: Support sharing irq lines between iommu queues Xu Lu
2024-07-01 7:29 ` Xu Lu [this message]
2024-07-01 8:47 ` [PATCH 1/1] " Tomasz Jeznach
2024-07-01 9:10 ` [External] " Xu Lu
2024-07-01 9:14 ` Xu Lu
2024-07-01 9:25 ` Tomasz Jeznach
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