Re: [RFC PATCH 4/9] cxl/pci: Map CXL PCIe ports' RAS registers

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

> >> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> >> index 0c79d9ce877c..51a4641fc9a6 100644
> >> --- a/drivers/cxl/mem.c
> >> +++ b/drivers/cxl/mem.c
> >> @@ -45,10 +45,39 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data)
> >>  	return 0;
> >>  }
> >>  
> >> +static bool cxl_dev_is_pci_type(struct device *dev, u32 pcie_type)  
> > Naming perhaps needs work to make it clear this is checking if
> > it's a CXL device of that type.
> > Also, seems like general functionality that belongs in core/pci.c or
> > similar.  
> 
> Any suggestions on what to use for the rename?
dev_is_pcie_of_type() perhaps?
The dvsec bit obviously is less general but might be bandled
separately with
	if ((dev_is_pcie_of_type(dport->dport_dev, PCI_EXP_TYPE_DOWNSTREAM) ||
	     dev_is_pcie_of_type(dport->dport_dev, PCI_EXP_TYPE_ROOT_PORT)) &&
	    cxl_dev_regloc(dport->dport_dev))

where 
cxl_dev_regloc() is that lookup and is also used in core/regs.c

Or something along those lines.