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AJvYcCUG3yH7169+gqqNbdbFqJzvWIBFBU6ElYsE+jBk01rT4IjSyZ6eRy9sir0f0OpCR3ZIh7Hz5/d4TPeBpZD17/4fbnmzlrSwTifyO/kP X-Gm-Message-State: AOJu0YyS5J0uL+nFGL9HQmDbBYyLdFCq4YlcilahRz7ycGZllDRzaw+J BuahSLdS3VzsZOeL3qJnxROlJpMVzxb6VDLqLzBIXc8Jtmr3Co0ra67EK5foJQ== X-Google-Smtp-Source: AGHT+IFfAmOh1vpybFa6ASP3tIwymsHJN+q/v+qmk1RVhTTsF5OCIrWZZWApJcwuyin0gArdkk3Wrw== X-Received: by 2002:a17:902:d4cd:b0:1f6:e20f:86b4 with SMTP id d9443c01a7336-1fb33f36fc1mr68382145ad.61.1720287603063; Sat, 06 Jul 2024 10:40:03 -0700 (PDT) Received: from thinkpad ([220.158.156.249]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fb14faa241sm70616845ad.110.2024.07.06.10.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jul 2024 10:40:02 -0700 (PDT) Date: Sat, 6 Jul 2024 23:09:54 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Jason Liu Subject: Re: [PATCH v6 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Message-ID: <20240706173954.GB3980@thinkpad> References: <20240617-pci2_upstream-v6-0-e0821238f997@nxp.com> <20240617-pci2_upstream-v6-2-e0821238f997@nxp.com> <20240629130525.GC5608@thinkpad> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Jul 01, 2024 at 02:32:59PM -0400, Frank Li wrote: > On Sat, Jun 29, 2024 at 06:35:25PM +0530, Manivannan Sadhasivam wrote: > > On Mon, Jun 17, 2024 at 04:16:38PM -0400, Frank Li wrote: > > > From: Richard Zhu > > > > > > Correct occasional MSI triggering failures in i.MX8MP PCIe EP by apply 64KB > > > hardware alignment requirement. > > > > > > MSI triggering fail if the outbound MSI memory region (ep->msi_mem) is not > > > aligned to 64KB. > > > > > > In dw_pcie_ep_init(): > > > > > > ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > > > epc->mem->window.page_size); > > > > > > > So this is an alignment restriction w.r.t iATU. In that case, we should be > > passing 'pci_epc_features::align' instead? > > pci_epc_features::align already set. > > pci_epc_mem_alloc_addr( > ... > align_size = ALIGN(size, mem->window.page_size); > order = pci_epc_mem_get_order(mem, align_size); > ... > } > > but pci_epc_mem_alloc_addr() align to page_size, instead of > pci_epc_features::align. > 'window.page_size' is set to what is passed as 'page_size' argument to pci_epc_mem_init(). In this case, 'ep->page_size' is passed which corresponds to size of pages that can be allocated within the memory window. Default value of 'ep->page_size' is PAGE_SIZE which is most likely 4K. So if your hardware cannot allocate 4K pages within the memory window, then it doesn't support splitting this OB region into 4K pages. But this has nothing to do with alignment AFAIU since epc_features::align is used for IB memory. This 'page_size' argument was introduced for some TI SoC that doesn't handle PAGE_SIZE splitting of OB memory window. Reference: 52c9285d4745 ("PCI: endpoint: Add support for configurable page size") Can you check if your SoC also suffers from the same limitation? If so, then you should modify the commit message to make it clear. - Mani -- மணிவண்ணன் சதாசிவம்