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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240716213131.6036-9-james.quinlan@broadcom.com> On Tue, Jul 16, 2024 at 05:31:23PM -0400, Jim Quinlan wrote: > We've been assuming that if an SOC has a "rescal" reset controller that we > should automatically invoke brcm_phy_cntl(...). This will not be true in > future SOCs, so we create a bool "has_phy" and adjust the cfg_data > appropriately (we need to give 7216 its own cfg_data structure instead of > sharing one). > In all commit messages, use imperative tone as per kernel documentation: "Describe your changes in imperative mood, e.g. "make xyzzy do frotz" instead of "[This patch] makes xyzzy do frotz" or "[I] changed xyzzy to do frotz", as if you are giving orders to the codebase to change its behaviour." > Signed-off-by: Jim Quinlan > Reviewed-by: Stanimir Varbanov > Reviewed-by: Florian Fainelli > --- > drivers/pci/controller/pcie-brcmstb.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index dfb404748ad8..8ab5a8ca05b4 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -222,6 +222,7 @@ enum pcie_type { > struct pcie_cfg_data { > const int *offsets; > const enum pcie_type type; > + const bool has_phy; 'has_phy' means the controller supports PHY and the new SoC doesn't have a PHY for the controller? - Mani -- மணிவண்ணன் சதாசிவம்