Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

Krzysztof Kozlowski
2025-09-10T07:16:24Z

On 09/09/2025 15:59, Anand Moon wrote:
> Hi Krzysztof, Marek,
>
> On Tue, 30 Jul 2024 at 20:32, Anand Moon <linux.amoon@gmail.com> wrote:
>>
>> Hi Krzysztof,
>>
>> On Tue, 30 Jul 2024 at 18:53, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>
>>> On 30/07/2024 15:20, Anand Moon wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>>
>>>>> On 30/07/2024 14:06, Anand Moon wrote:
>>>>>> Hi Marek,
>>>>>>
>>>>>> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 30.07.2024 11:13, Anand Moon wrote:
>>>>>>>> As per the Exynos 5422 user manual add missing cache information to
>>>>>>>> the Exynos542x SoC.
>>>>>>>>
>>>>>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
>>>>>>>> 32 KB of L1 data cache available.
>>>>>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
>>>>>>>> 32 KB of L1 data cache available.
>>>>>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
>>>>>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
>>>>>>>>
>>>>>>>> Features:
>>>>>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
>>>>>>>> L2 cache snooping capability. This hardware automatic L2 cache
>>>>>>>> snooping removes the efforts of synchronizing the contents of the
>>>>>>>> two L2 caches in core switching event.
>>>>>>>>
>>>>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>>>>>>
>>>>>>>
>>>>>>> The provided values are not correct. Please refer to commit 5f41f9198f29
>>>>>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
>>>>>>> cores"), which adds workaround for different l1 icache line size between
>>>>>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
>>>>>>> boards.
>>>>>>>
>>>>>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
>>>>>> This patch is just updating the cache size for CPU for big.litle architecture..
>>>>>>
>>>>>
>>>>> Let me get it right. Marek's comment was that you used wrong values.
>>>>> Marek also provided rationale for this. Now your reply is that you
>>>>> update cache size? Sorry, I fail how you address Marek's comment.
>>>>>
>>>>> Do not repeat what the patch is doing. We all can see it. Instead
>>>>> respond to the comment with some sort of arguments.
>>>>>
>>>>
>>>> Ok, If I am not wrong icache_size is hard-coded in the above commit.
>>>>
>>>> +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
>>>> +.globl icache_size
>>>> + .data
>>>> + .align 2
>>>> +icache_size:
>>>> + .long 64
>>>> + .text
>>>> +#endif
>>>>
>>>> In the check_cpu_icache_size function, we read the control reg
>>>> and recalculate the icache_size.
>>>> if there mismatch we re-apply the Icache_size,
>>>>
>>>> So dts passed values do not apply over here,
>>>
>>> So you provide incorrect values in terms of them being ignored? Then do
>>> not provide at all.
>>>
>> I will drop the icache and dcache values and just pass the L2_a7 and
>> L2_a15, value
>> Is this ok for you?
>>
>> Earlier, I have tried to verify this information in /sys and /proc
>> to verify the changes as ARM does not populate this information.
>>
> Here's an article that provides detailed insights into the cache feature.
> [0] http://jake.dothome.co.kr/cache4/

Here is Korean Wikipedia article about Sugar glider:
https://ko.wikipedia.org/wiki/%EC%9C%A0%EB%8C%80%ED%95%98%EB%8A%98%EB%8B%A4%EB%9E%8C%EC%A5%90

I guess we are putting now random references in Korean to our emails.

>
> The values associated with L1 and L2 caches indicate their respective sizes,
> as specified in the ARM Technical Reference Manual (TRM) below.
>
> Cortex-A15 L2 cache controller
> [0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller
>
> Cortex-A7 L2 cache controller
> [1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller
>
> These changes help define a fixed cache size, ensuring that active pages
> are mapped correctly within the expected cache boundaries.

As with many previous attempts, you do not understand comments and
questions and you do not reply to them. This makes conversation pointless.

To prove it:

1. No one asks for performance numbers.
2. You give performance numbers.

I am dropping this patch because you did not address actual comments. I
also do not plan to give thorough review to other of your patches,
because you wasted a lot of my time in the past and this example here
proves you keep wasting.

Best regards,
Krzysztof