Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

Marek Szyprowski
2024-07-30T11:44:43Z

On 30.07.2024 11:13, Anand Moon wrote:
> As per Exynos 5422 user manual add missing cache information to
> the Exynos542x SoC.
>
> - Each Cortex-A7 core has 32 KB of instruction cache and
> 32 KB of L1 data cache available.
> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> 32 KB of L1 data cache available.
> - The little (A7) cluster has 512 KB of unified L2 cache available.
> - The big (A15) cluster has 2 MB of unified L2 cache available.
>
> Features:
> - Exynos 5422 support cache coherency interconnect (CCI) bus with
> L2 cache snooping capability. This hardware automatic L2 cache
> snooping removes the efforts of synchronizing the contents of the
> two L2 caches in core switching event.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>

The provided values are not correct. Please refer to commit 5f41f9198f29
("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
cores"), which adds workaround for different l1 icache line size between
big and little CPUs. This workaround gets enabled on all Exynos542x/5800
boards.

> ---
> .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> index 412a0bb4b988..9b9b2bdfb522 100644
> --- a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> @@ -59,6 +59,13 @@ cpu0: cpu@100 {
> reg = <0x100>;
> clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a7>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -72,6 +79,13 @@ cpu1: cpu@101 {
> reg = <0x101>;
> clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a7>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -85,6 +99,13 @@ cpu2: cpu@102 {
> reg = <0x102>;
> clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a7>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -98,6 +119,13 @@ cpu3: cpu@103 {
> reg = <0x103>;
> clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a7>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -111,6 +139,13 @@ cpu4: cpu@0 {
> reg = <0x0>;
> clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a15>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -124,6 +159,13 @@ cpu5: cpu@1 {
> reg = <0x1>;
> clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a15>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -137,6 +179,13 @@ cpu6: cpu@2 {
> reg = <0x2>;
> clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a15>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> @@ -150,12 +199,37 @@ cpu7: cpu@3 {
> reg = <0x3>;
> clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> + next-level-cache = <&L2_a15>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> #cooling-cells = <2>; /* min followed by max */
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <310>;
> };
> +
> + L2_a7: l2-cache-cluster0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + cache-size = <0x80000>; /* L2. 512 KB */
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + };
> +
> + L2_a15: l2-cache-cluster1 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + cache-size = <0x200000>; /* L2, 2M */
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + };
> };
> };
>

Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland