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* [PATCH AUTOSEL 6.10 001/121] drm/amd/display: Enable RCO for PHYSYMCLK in DCN35
@ 2024-07-31 23:58 Sasha Levin
  2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 002/121] drm/amd/display: Assign linear_pitch_alignment even for VM Sasha Levin
                   ` (119 more replies)
  0 siblings, 120 replies; 123+ messages in thread
From: Sasha Levin @ 2024-07-31 23:58 UTC (permalink / raw)
  To: linux-kernel, stable
  Cc: Daniel Miess, Roman Li, Charlene Liu, Wayne Lin, Daniel Wheeler,
	Alex Deucher, Sasha Levin, harry.wentland, sunpeng.li,
	Rodrigo.Siqueira, christian.koenig, Xinhui.Pan, airlied, daniel,
	aric.cyr, hamza.mahfooz, nicholas.kazlauskas, alvin.lee2,
	Qingqing.Zhuo, aurabindo.pillai, chiahsuan.chung, dillon.varone,
	yi-lchen, ahmed.ahmed, syed.hassan, harikrishna.revalla,
	alex.hung, sungjoon.kim, michael.strauss, allen.pan, duncan.ma,
	danny.wang, amd-gfx, dri-devel

From: Daniel Miess <daniel.miess@amd.com>

[ Upstream commit f2303026a5b6327247ba61152d00199b2d1be294 ]

[Why & How]
Enable root clock optimization for PHYSYMCLK and only
disable it when it's actively being used

v2:  Fix array-index-out-of-bounds in dcn35_calc_blocks_to_gate

Reviewed-by: Roman Li <roman.li@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 .../gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c | 45 -------------------
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 32 +++++++++++++
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h   |  2 +
 .../amd/display/dc/hwss/dcn35/dcn35_init.c    |  1 +
 .../amd/display/dc/hwss/dcn351/dcn351_init.c  |  1 +
 .../display/dc/hwss/hw_sequencer_private.h    |  4 ++
 7 files changed, 41 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3c33c3bcbe2cb..fe0025f2167fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -701,6 +701,7 @@ enum pg_hw_pipe_resources {
 	PG_OPTC,
 	PG_DPSTREAM,
 	PG_HDMISTREAM,
+	PG_PHYSYMCLK,
 	PG_HW_PIPE_RESOURCES_NUM_ELEMENT
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
index 58dd3c5bbff09..024dcf3057a05 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
@@ -451,32 +451,22 @@ static void dccg35_set_physymclk_root_clock_gating(
 	case 0:
 		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
 				PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
-//		REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//				PHYA_REFCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
 		break;
 	case 1:
 		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
 				PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
-//		REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//				PHYB_REFCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
 		break;
 	case 2:
 		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
 				PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
-//		REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//				PHYC_REFCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
 		break;
 	case 3:
 		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
 				PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
-//		REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//				PHYD_REFCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
 		break;
 	case 4:
 		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
 				PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
-//		REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//				PHYE_REFCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
@@ -499,16 +489,10 @@ static void dccg35_set_physymclk(
 			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
 					PHYASYMCLK_EN, 1,
 					PHYASYMCLK_SRC_SEL, clk_src);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYA_REFCLK_ROOT_GATE_DISABLE, 0);
 		} else {
 			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
 					PHYASYMCLK_EN, 0,
 					PHYASYMCLK_SRC_SEL, 0);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYA_REFCLK_ROOT_GATE_DISABLE, 1);
 		}
 		break;
 	case 1:
@@ -516,16 +500,10 @@ static void dccg35_set_physymclk(
 			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
 					PHYBSYMCLK_EN, 1,
 					PHYBSYMCLK_SRC_SEL, clk_src);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYB_REFCLK_ROOT_GATE_DISABLE, 0);
 		} else {
 			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
 					PHYBSYMCLK_EN, 0,
 					PHYBSYMCLK_SRC_SEL, 0);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYB_REFCLK_ROOT_GATE_DISABLE, 1);
 		}
 		break;
 	case 2:
@@ -533,16 +511,10 @@ static void dccg35_set_physymclk(
 			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
 					PHYCSYMCLK_EN, 1,
 					PHYCSYMCLK_SRC_SEL, clk_src);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYC_REFCLK_ROOT_GATE_DISABLE, 0);
 		} else {
 			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
 					PHYCSYMCLK_EN, 0,
 					PHYCSYMCLK_SRC_SEL, 0);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYC_REFCLK_ROOT_GATE_DISABLE, 1);
 		}
 		break;
 	case 3:
@@ -550,16 +522,10 @@ static void dccg35_set_physymclk(
 			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
 					PHYDSYMCLK_EN, 1,
 					PHYDSYMCLK_SRC_SEL, clk_src);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYD_REFCLK_ROOT_GATE_DISABLE, 0);
 		} else {
 			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
 					PHYDSYMCLK_EN, 0,
 					PHYDSYMCLK_SRC_SEL, 0);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYD_REFCLK_ROOT_GATE_DISABLE, 1);
 		}
 		break;
 	case 4:
@@ -567,16 +533,10 @@ static void dccg35_set_physymclk(
 			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
 					PHYESYMCLK_EN, 1,
 					PHYESYMCLK_SRC_SEL, clk_src);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYE_REFCLK_ROOT_GATE_DISABLE, 0);
 		} else {
 			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
 					PHYESYMCLK_EN, 0,
 					PHYESYMCLK_SRC_SEL, 0);
-//			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4,
-//						PHYE_REFCLK_ROOT_GATE_DISABLE, 1);
 		}
 		break;
 	default:
@@ -714,11 +674,6 @@ void dccg35_init(struct dccg *dccg)
 			dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);
 		}
 
-	if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
-		for (otg_inst = 0; otg_inst < 5; otg_inst++)
-			dccg35_set_physymclk_root_clock_gating(dccg, otg_inst,
-					false);
-
 	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
 		for (otg_inst = 0; otg_inst < 4; otg_inst++)
 			dccg35_set_dppclk_root_clock_gating(dccg, otg_inst, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index dcced89c07b38..5f60da72c6f58 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -506,6 +506,17 @@ void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hp
 	}
 }
 
+void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on)
+{
+	if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+		return;
+
+	if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {
+		hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(
+			hws->ctx->dc->res_pool->dccg, phy_inst, clock_on);
+	}
+}
+
 void dcn35_dsc_pg_control(
 		struct dce_hwseq *hws,
 		unsigned int dsc_inst,
@@ -1041,6 +1052,13 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
 		if (pipe_ctx->stream_res.hpo_dp_stream_enc)
 			update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;
 	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;
+		if (dc->links[i]->type != dc_connection_none)
+			update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;
+	}
+
 	/*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/
 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
@@ -1138,6 +1156,10 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
 		}
 	}
 
+	for (i = 0; i < dc->link_count; i++)
+		if (dc->links[i]->type != dc_connection_none)
+			update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;
+
 	for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {
 		if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] &&
 				dc->res_pool->hpo_dp_stream_enc[i]) {
@@ -1288,6 +1310,11 @@ void dcn35_root_clock_control(struct dc *dc,
 					dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
 		}
 
+		for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)
+			if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])
+				if (dc->hwseq->funcs.physymclk_root_clock_control)
+					dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);
+
 	}
 	for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
 		if (update_state->pg_pipe_res_update[PG_DSC][i]) {
@@ -1313,6 +1340,11 @@ void dcn35_root_clock_control(struct dc *dc,
 					dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
 		}
 
+		for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)
+			if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])
+				if (dc->hwseq->funcs.physymclk_root_clock_control)
+					dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);
+
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index f0ea7d1511ae6..e27b3609020ff 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -39,6 +39,8 @@ void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst,
 
 void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on);
 
+void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);
+
 void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
 
 void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 199781233fd5f..987e09d9246e4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -148,6 +148,7 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
 	.enable_power_gating_plane = dcn35_enable_power_gating_plane,
 	.dpp_root_clock_control = dcn35_dpp_root_clock_control,
 	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
+	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn35_update_odm,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index a53092cd619b1..2e0d23ae8fee5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -147,6 +147,7 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
 	.enable_power_gating_plane = dcn35_enable_power_gating_plane,
 	.dpp_root_clock_control = dcn35_dpp_root_clock_control,
 	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
+	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn35_update_odm,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
index 341219cf41442..9553a7d34c3e9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
@@ -124,6 +124,10 @@ struct hwseq_private_funcs {
 			struct dce_hwseq *hws,
 			unsigned int dpp_inst,
 			bool clock_on);
+	void (*physymclk_root_clock_control)(
+			struct dce_hwseq *hws,
+			unsigned int phy_inst,
+			bool clock_on);
 	void (*dpp_pg_control)(struct dce_hwseq *hws,
 			unsigned int dpp_inst,
 			bool power_on);
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 123+ messages in thread

end of thread, other threads:[~2024-08-27 12:22 UTC | newest]

Thread overview: 123+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-31 23:58 [PATCH AUTOSEL 6.10 001/121] drm/amd/display: Enable RCO for PHYSYMCLK in DCN35 Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 002/121] drm/amd/display: Assign linear_pitch_alignment even for VM Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 003/121] drm/amdgpu: fix overflowed array index read warning Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 004/121] drm/amdgpu/pm: Check the return value of smum_send_msg_to_smc Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 005/121] drm/amd/pm: fix warning using uninitialized value of max_vid_step Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 006/121] drm/amd/pm: Fix negative array index read Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 007/121] drm/amd/pm: fix the Out-of-bounds read warning Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 008/121] drm/amdgpu: fix uninitialized scalar variable warning Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 009/121] drm/amd/display: Ensure array index tg_inst won't be -1 Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 010/121] drm/amd/display: Check gpio_id before used as array index Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 011/121] drm/amd/display: Add NULL pointer and OVERRUN check within amdgpu_dm irq register Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 012/121] drm/amd/display: Stop amdgpu_dm initialize when stream nums greater than 6 Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 013/121] drm/amd/display: Stop amdgpu_dm initialize when link nums greater than max_links Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 014/121] drm/amd/display: Fix incorrect size calculation for loop Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 015/121] drm/amd/display: Check index for aux_rd_interval before using Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 016/121] drm/amd/display: Add missing NULL pointer check within dpcd_extend_address_range Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 017/121] drm/amd/display: Add array index check for hdcp ddc access Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 018/121] drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[] Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 019/121] drm/amd/display: Skip updating link encoder for unknown eng_id Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 020/121] drm/amd/display: Check msg_id before processing transcation Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 021/121] drm/amd/display: Release state memory if amdgpu_dm_create_color_properties fail Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 022/121] drm/amd/display: Check link_index before accessing dc->links[] Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 023/121] drm/amd/display: Add otg_master NULL check within resource_log_pipe_topology_update Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 024/121] drm/amd/display: Fix Coverity INTERGER_OVERFLOW within construct_integrated_info Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 025/121] drm/amd/display: Fix Coverity INTEGER_OVERFLOW within dal_gpio_service_create Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 026/121] drm/amd/display: Release clck_src memory if clk_src_construct fails Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 027/121] drm/amd/display: Spinlock before reading event Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 028/121] drm/amd/display: Fix Coverity INTEGER_OVERFLOW within decide_fallback_link_setting_max_bw_policy Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 029/121] drm/amd/display: Skip inactive planes within ModeSupportAndSystemConfiguration Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 030/121] drm/amd/display: Fix index may exceed array range within fpu_update_bw_bounding_box Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 031/121] drm/amd/amdgpu: Check tbo resource pointer Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 032/121] drm/amdgpu: Fix out-of-bounds write warning Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 033/121] drm/amdkfd: Check debug trap enable before write dbg_ev_file Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 034/121] drm/amdgpu: Fix out-of-bounds read of df_v1_7_channel_number Sasha Levin
2024-08-27 12:22   ` Pavel Machek
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 035/121] drm/amdgpu: fix ucode out-of-bounds read warning Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 036/121] drm/amdgpu: fix mc_data " Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 037/121] drm/amdkfd: Reconcile the definition and use of oem_id in struct kfd_topology_device Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 038/121] wifi: ath12k: initialize 'ret' in ath12k_qmi_load_file_target_mem() Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 039/121] wifi: ath11k: initialize 'ret' in ath11k_qmi_load_file_target_mem() Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 040/121] wifi: ath12k: initialize 'ret' in ath12k_dp_rxdma_ring_sel_config_wcn7850() Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 041/121] drm/amdgpu/pm: Check input value for CUSTOM profile mode setting on legacy SOCs Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 042/121] drm/amdgpu/pm: Check input value for power profile setting on smu11, smu13 and smu14 Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 043/121] drm/amdgpu/vcn: remove irq disabling in vcn 5 suspend Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 044/121] drm/amdgpu: Fix the warning division or modulo by zero Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 045/121] drm/amdgpu: fix dereference after null check Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 046/121] drm/amdgpu: fix the waring dereferencing hive Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 047/121] drm/amdgpu: the warning dereferencing obj for nbio_v7_4 Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 048/121] drm/amd/display: Fix pipe addition logic in calc_blocks_to_ungate DCN35 Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 049/121] drm/amdgpu: update type of buf size to u32 for eeprom functions Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 050/121] drm/xe/mmio: move mmio_fini over to devm Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 051/121] drm/xe: reset mmio mappings with devm Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 052/121] wifi: iwlwifi: fw: avoid bad FW config on RXQ DMA failure Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 053/121] drm/xe: Fix xe_pm_runtime_get_if_active return Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 054/121] cpufreq: scmi: Avoid overflow of target_freq in fast switch Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 055/121] bpf, net: Use DEV_STAT_INC() Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 056/121] PCI: al: Check IORESOURCE_BUS existence during probe Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 057/121] remoteproc: mediatek: Zero out only remaining bytes of IPI buffer Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 058/121] wifi: iwlwifi: mvm: use only beacon BSS load for active links Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 059/121] hwspinlock: Introduce hwspin_lock_bust() Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 060/121] soc: qcom: smem: Add qcom_smem_bust_hwspin_lock_by_host() Sasha Levin
2024-07-31 23:59 ` [PATCH AUTOSEL 6.10 061/121] remoteproc: qcom_q6v5_pas: Add hwspinlock bust on stop Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 062/121] gpiolib: cdev: Add INIT_KFIFO() for linereq events Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 063/121] pwm: xilinx: Fix u32 overflow issue in 32-bit width PWM mode Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 064/121] drm/amdgu: fix Unintentional integer overflow for mall size Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 065/121] smack: tcp: ipv4, fix incorrect labeling Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 066/121] drm/bridge: tc358767: Check if fully initialized before signalling HPD event via IRQ Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 067/121] drm/xe: Check valid domain is passed in xe_force_wake_ref Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 068/121] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 069/121] thermal: trip: Use READ_ONCE() for lockless access to trip properties Sasha Levin
2024-08-01 10:23   ` Rafael J. Wysocki
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 070/121] EDAC/amd64: Check return value of amd_smn_read() Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 071/121] hwmon: (k10temp) " Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 072/121] wifi: cfg80211: make hash table duplicates more survivable Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 073/121] driver: iio: add missing checks on iio_info's callback access Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 074/121] drm/amd/display: added NULL check at start of dc_validate_stream Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 075/121] drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAX Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 076/121] drm/amd/display: Remove register from DCN35 DMCUB diagnostic collection Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 077/121] drm/amd/display: use preferred link settings for dp signal only Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 078/121] drm/amd/display: Disable DMCUB timeout for DCN35 Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 079/121] drm/amd/display: Avoid overflow from uint32_t to uint8_t Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 080/121] drm/amd/display: Check BIOS images before it is used Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 081/121] drm/amd/display: Skip wbscl_set_scaler_filter if filter is null Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 082/121] io_uring/io-wq: make io_wq_work flags atomic Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 083/121] fou: remove warn in gue_gro_receive on unsupported protocol Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 084/121] ALSA: vmaster: Return error for invalid input values Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 085/121] ALSA: control: Apply sanity check of input values for user elements Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 086/121] wifi: ath12k: fix uninitialize symbol error on ath12k_peer_assoc_h_he() Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 087/121] wifi: ath12k: fix firmware crash due to invalid peer nss Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 088/121] drm/amd/display: Check UnboundedRequestEnabled's value Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 089/121] x86/alternatives: Make FineIBT mode Kconfig selectable Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 090/121] ELF: fix kernel.randomize_va_space double read Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 091/121] accel/habanalabs/gaudi2: unsecure edma max outstanding register Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 092/121] x86/kmsan: Fix hook for unaligned accesses Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 093/121] iommu: sun50i: allocate page tables from below 4 GiB Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 094/121] udf: Avoid excessive partition lengths Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 095/121] riscv: mm: Take memory hotplug read-lock during kernel page table dump Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 096/121] usb: uas: set host status byte on data completion error Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 097/121] drm/amdgpu: Fix register access violation Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 098/121] drm/amd/display: Run DC_LOG_DC after checking link->link_enc Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 099/121] drm/amd/display: Check HDCP returned status Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 100/121] drm/amd/display: Validate function returns Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 101/121] drm/amdgpu: add missing error handling in function amdgpu_gmc_flush_gpu_tlb_pasid Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 102/121] powerpc/rtas: Prevent Spectre v1 gadget construction in sys_rtas() Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 103/121] drm/amd/display: Check denominator pbn_div before used Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 104/121] drm/amd/display: Check denominator crb_pipes " Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 105/121] phy: zynqmp: Take the phy mutex in xlate Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 106/121] cgroup: Protect css->cgroup write under css_set_lock Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 107/121] um: line: always fill *error_out in setup_one_line() Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 108/121] devres: Initialize an uninitialized struct member Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 109/121] wifi: iwlwifi: mvm: don't send an ROC command with max_delay = 0 Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 110/121] pci/hotplug/pnv_php: Fix hotplug driver crash on Powernv Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 111/121] virtio_ring: fix KMSAN error for premapped mode Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 112/121] wifi: rtw88: usb: schedule rx work after everything is set up Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 113/121] scsi: pm80xx: Set phy->enable_completion only when we wait for it Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 114/121] block: factor out a blk_write_zeroes_limit helper Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 115/121] hwmon: (lm95234) Fix underflows seen when writing limit attributes Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 116/121] hwmon: (nct6775-core) " Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 117/121] hwmon: (w83627ehf) " Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 118/121] libbpf: Add NULL checks to bpf_object__{prev_map,next_map} Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 119/121] wifi: mac80211_hwsim: fix warning Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 120/121] wifi: mwifiex: Do not return unused priv in mwifiex_get_priv_by_id() Sasha Levin
2024-08-01  0:00 ` [PATCH AUTOSEL 6.10 121/121] i3c: mipi-i3c-hci: Error out instead on BUG_ON() in IBI DMA setup Sasha Levin

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