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AJvYcCXDbNNDprjrRx2b05p7PpVa+jNOWahnqxY5ZgAUXZpY+v+YlL2f8t4H3e1Q/eiKszTcEKb9gugJWaQvGG27HnBH2bX8w+5KEN47ZAgo X-Gm-Message-State: AOJu0Yz3kR6PBPvCcRbKKSv7P/Oz3Su3yQOiCR5FcWn8H6MJ3IqrYNM7 0d4FnrdGyiawDnL1sghnfesKHWxcTzBoqe012XJV9HMaLk+7HL29WHNSlJqdYA== X-Google-Smtp-Source: AGHT+IHeBBB9HZdLy26QExMAW0qOHs0KBnu6vbFxqKF47qSsZ46yR0Ql9vqC7kMPYTC0pjfebwTrUA== X-Received: by 2002:a05:6a00:170b:b0:710:bd4b:8b96 with SMTP id d2e1a72fcca58-710bd4b964emr856276b3a.28.1722999913813; Tue, 06 Aug 2024 20:05:13 -0700 (PDT) Received: from thinkpad ([120.60.72.69]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7b762e9f5cdsm7616512a12.2.2024.08.06.20.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Aug 2024 20:05:13 -0700 (PDT) Date: Wed, 7 Aug 2024 08:35:02 +0530 From: Manivannan Sadhasivam To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v5 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Message-ID: <20240807030502.GI3412@thinkpad> References: <20240731222831.14895-1-james.quinlan@broadcom.com> <20240731222831.14895-9-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240731222831.14895-9-james.quinlan@broadcom.com> On Wed, Jul 31, 2024 at 06:28:22PM -0400, Jim Quinlan wrote: > Add a "has_phy" field indicating that the internal phy has SW control that > requires configuration. Some previous chips only required the firing of > the "rescal" reset controller. This change requires us to give the 7216 > SoC its own cfg_data structure. > > Signed-off-by: Jim Quinlan Reviewed-by: Manivannan Sadhasivam - Mani > Reviewed-by: Stanimir Varbanov > Reviewed-by: Florian Fainelli > --- > drivers/pci/controller/pcie-brcmstb.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 1ae66c639186..4659208ae8da 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -222,6 +222,7 @@ enum pcie_type { > struct pcie_cfg_data { > const int *offsets; > const enum pcie_type type; > + const bool has_phy; > void (*perst_set)(struct brcm_pcie *pcie, u32 val); > void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); > }; > @@ -272,6 +273,7 @@ struct brcm_pcie { > void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); > struct subdev_regulators *sr; > bool ep_wakeup_capable; > + bool has_phy; > }; > > static inline bool is_bmips(const struct brcm_pcie *pcie) > @@ -1311,12 +1313,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) > > static inline int brcm_phy_start(struct brcm_pcie *pcie) > { > - return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; > + return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; > } > > static inline int brcm_phy_stop(struct brcm_pcie *pcie) > { > - return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; > + return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; > } > > static void brcm_pcie_turn_off(struct brcm_pcie *pcie) > @@ -1559,12 +1561,20 @@ static const struct pcie_cfg_data bcm2711_cfg = { > .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, > }; > > +static const struct pcie_cfg_data bcm7216_cfg = { > + .offsets = pcie_offset_bcm7278, > + .type = BCM7278, > + .perst_set = brcm_pcie_perst_set_7278, > + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, > + .has_phy = true, > +}; > + > static const struct of_device_id brcm_pcie_match[] = { > { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, > { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, > { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, > { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, > - { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, > + { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg }, > { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, > { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, > { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg }, > @@ -1612,6 +1622,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) > pcie->type = data->type; > pcie->perst_set = data->perst_set; > pcie->bridge_sw_init_set = data->bridge_sw_init_set; > + pcie->has_phy = data->has_phy; > > pcie->base = devm_platform_ioremap_resource(pdev, 0); > if (IS_ERR(pcie->base)) > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம்