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AJvYcCVp/oHB10/3cwgJoxiNZVLCUyUfR/PW/1qe6VsmbS33XJk9dm+svbce0Pjj1L++Bv8fQVjSFbbUZXe2uCypb//4B65grayKwuXcbfip X-Gm-Message-State: AOJu0Yz8dwRlgl0y4YoGqyJb8/lvi3phYVzEqkTS6TOkEMmC9yeskhFh DwF/BLeMUhRT/+sObrY+XV4BcSunxTdLbrVh+WO5XdIPFJ+IGzGq1G76B7UCmw== X-Google-Smtp-Source: AGHT+IE+2bxt0RWYDzoa/0717PVsVp/VC5L53fxD/frfjlYdSeFOHQvtM70NjBfd+Nz1QbuAWz1Ktg== X-Received: by 2002:a05:6a00:6f0f:b0:706:67c9:16d0 with SMTP id d2e1a72fcca58-7106d0812eemr17260571b3a.26.1723039982533; Wed, 07 Aug 2024 07:13:02 -0700 (PDT) Received: from thinkpad ([120.60.60.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7106ec06a25sm8462024b3a.33.2024.08.07.07.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Aug 2024 07:13:02 -0700 (PDT) Date: Wed, 7 Aug 2024 19:42:48 +0530 From: Manivannan Sadhasivam To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v5 12/12] PCI: brcmstb: Enable 7712 SOCs Message-ID: <20240807141248.GL3412@thinkpad> References: <20240731222831.14895-1-james.quinlan@broadcom.com> <20240731222831.14895-13-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240731222831.14895-13-james.quinlan@broadcom.com> On Wed, Jul 31, 2024 at 06:28:26PM -0400, Jim Quinlan wrote: > The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). > It has one PCIe controller with a single port, supports gen2 > and one lane only. The current revision of the chip is "C0" > or "C1". > > Signed-off-by: Jim Quinlan Reviewed-by: Manivannan Sadhasivam - Mani > Reviewed-by: Stanimir Varbanov > Reviewed-by: Florian Fainelli > --- > drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 4623b70f9ad8..44b323a13357 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -1202,6 +1202,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) > const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; > u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ > > + /* 7712 does not have this (RGR1) timer */ > + if (pcie->soc_base == BCM7712) > + return; > + > /* Each unit in timeout register is 1/216,000,000 seconds */ > writel(216 * timeout_us, pcie->base + REG_OFFSET); > } > @@ -1673,6 +1677,13 @@ static const int pcie_offsets_bmips_7425[] = { > [PCIE_INTR2_CPU_BASE] = 0x4300, > }; > > +static const int pcie_offset_bcm7712[] = { > + [EXT_CFG_INDEX] = 0x9000, > + [EXT_CFG_DATA] = 0x9004, > + [PCIE_HARD_DEBUG] = 0x4304, > + [PCIE_INTR2_CPU_BASE] = 0x4400, > +}; > + > static const struct pcie_cfg_data generic_cfg = { > .offsets = pcie_offsets, > .soc_base = GENERIC, > @@ -1738,6 +1749,14 @@ static const struct pcie_cfg_data bcm7216_cfg = { > .num_inbound_wins = 3, > }; > > +static const struct pcie_cfg_data bcm7712_cfg = { > + .offsets = pcie_offset_bcm7712, > + .perst_set = brcm_pcie_perst_set_7278, > + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, > + .soc_base = BCM7712, > + .num_inbound_wins = 10, > +}; > + > static const struct of_device_id brcm_pcie_match[] = { > { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, > { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, > @@ -1747,6 +1766,7 @@ static const struct of_device_id brcm_pcie_match[] = { > { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, > { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, > { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg }, > + { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg }, > {}, > }; > > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம்