[PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[412574090]

From: weiyufeng <weiyufeng@kylinos.cn>

PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
this whilst doing Gen6 accesses.

Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
---
 include/uapi/linux/pci_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 94c00996e633..cc875534dae1 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -741,6 +741,7 @@
 #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
 #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
 #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
+#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */
 #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
 #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
 
-- 
2.25.1

Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[Ilpo Järvinen]

On Tue, 6 Aug 2024, 412574090@163.com wrote:

> From: weiyufeng <weiyufeng@kylinos.cn>
> 
> PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> this whilst doing Gen6 accesses.
> 
> Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> ---
>  include/uapi/linux/pci_regs.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 94c00996e633..cc875534dae1 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -741,6 +741,7 @@
>  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
>  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
>  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */
>  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */

These should be in numerical order.

>  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE

This was not adapted??

-- 
 i.

Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[Bjorn Helgaas]

On Tue, Aug 06, 2024 at 10:27:46AM +0800, 412574090@163.com wrote:
> From: weiyufeng <weiyufeng@kylinos.cn>
> 
> PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> this whilst doing Gen6 accesses.
> 
> Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> ---
>  include/uapi/linux/pci_regs.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 94c00996e633..cc875534dae1 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -741,6 +741,7 @@
>  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
>  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
>  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */

It probably makes sense to add this (with the corrections noted by
Ilpo), but I *would* like to see where it's used.

I asked a similar question at
https://lore.kernel.org/all/20230531095713.293229-1-ben.dooks@codethink.co.uk/
when we added PCI_EXT_CAP_ID_PL_32GT, but never got a specific
response.  I don't really want to end up with drivers doing their own
thing if it's something that could be done in the PCI core and shared.

>  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
>  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
>  
> -- 
> 2.25.1
> 

Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[412574090]

> On Tue, Aug 06, 2024 at 10:27:46AM +0800, 412574090@163.com wrote:
> > From: weiyufeng <weiyufeng@kylinos.cn>
> > 
> > PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> > ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> > this whilst doing Gen6 accesses.
> > 
> > Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> > ---
> >  include/uapi/linux/pci_regs.h | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > index 94c00996e633..cc875534dae1 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -741,6 +741,7 @@
> >  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
> >  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
> >  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> > +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */
>
> It probably makes sense to add this (with the corrections noted by
> Ilpo), but I *would* like to see where it's used.
>
> I asked a similar question at
> https://lore.kernel.org/all/20230531095713.293229-1-ben.dooks@codethink.co.uk/
> when we added PCI_EXT_CAP_ID_PL_32GT, but never got a specific
> response.  I don't really want to end up with drivers doing their own
> thing if it's something that could be done in the PCI core and shared.
>
PCI_EXT_CAP_ID_PL_32GT and PCI_EXT_CAP_ID_PL_64GT have not used now,but 
PCI_EXT_CAP_ID_PL_16GT have usage example,in drivers/pci/controller/dwc/pcie-tegra194.c
function config_gen3_gen4_eq_presets():

offset = dw_pcie_find_ext_capability(pci,
				     PCI_EXT_CAP_ID_PL_16GT) +
		PCI_PL_16GT_LE_CTRL;

PCI_EXT_CAP_ID_PL_32GT and PCI_EXT_CAP_ID_PL_64GT could be used while need to
get this similar attribute。

> >  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
> >  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
> >  
> > -- 
> > 2.25.1
> > 
--
Thanks,

weiyufeng

Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[412574090]

> On Tue, 6 Aug 2024, 412574090@163.com wrote:
>
> > From: weiyufeng <weiyufeng@kylinos.cn>
> 
> > PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> > ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> > this whilst doing Gen6 accesses.
> > 
> > Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> > ---
> >  include/uapi/linux/pci_regs.h | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > index 94c00996e633..cc875534dae1 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -741,6 +741,7 @@
> >  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
> >  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
> >  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> > +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */
> >  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */

> These should be in numerical order.
In PCIe r6.0, PCI_EXT_CAP_ID_PL_64GT value is 0x31.

> >  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE

> This was not adapted??
PCIe r6.0, sec 7.7.7.1 have this definition。
--
Thanks,

weiyufeng

Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[Jonathan Cameron]

On Thu,  8 Aug 2024 10:12:39 +0800
412574090@163.com wrote:

> > On Tue, Aug 06, 2024 at 10:27:46AM +0800, 412574090@163.com wrote:  
> > > From: weiyufeng <weiyufeng@kylinos.cn>
> > > 
> > > PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> > > ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> > > this whilst doing Gen6 accesses.
> > > 
> > > Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> > > ---
> > >  include/uapi/linux/pci_regs.h | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > > index 94c00996e633..cc875534dae1 100644
> > > --- a/include/uapi/linux/pci_regs.h
> > > +++ b/include/uapi/linux/pci_regs.h
> > > @@ -741,6 +741,7 @@
> > >  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
> > >  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
> > >  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> > > +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */  
> >
> > It probably makes sense to add this (with the corrections noted by
> > Ilpo), but I *would* like to see where it's used.
> >
> > I asked a similar question at
> > https://lore.kernel.org/all/20230531095713.293229-1-ben.dooks@codethink.co.uk/
> > when we added PCI_EXT_CAP_ID_PL_32GT, but never got a specific
> > response.  I don't really want to end up with drivers doing their own
> > thing if it's something that could be done in the PCI core and shared.
> >  
> PCI_EXT_CAP_ID_PL_32GT and PCI_EXT_CAP_ID_PL_64GT have not used now,but 
> PCI_EXT_CAP_ID_PL_16GT have usage example,in drivers/pci/controller/dwc/pcie-tegra194.c
> function config_gen3_gen4_eq_presets():
> 
> offset = dw_pcie_find_ext_capability(pci,
> 				     PCI_EXT_CAP_ID_PL_16GT) +
> 		PCI_PL_16GT_LE_CTRL;
> 
> PCI_EXT_CAP_ID_PL_32GT and PCI_EXT_CAP_ID_PL_64GT could be used while need to
> get this similar attribute。

I'll bite.  In PCI_EXTE_CAP_ID_PL_32GT PCIe 6.1 which I happen to have
open has some writeable fields in the control register.  So
kind of fair enough a driver might write them.  In my view we should
probably have waited for such a use to turn up.

The Physical Layer 64.0 GT/s Extended Capability control register is
entirely reserved. So as of now, I don't see a use for this capability
until the PCIe spec adds something.

> 
> > >  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
> > >  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
> > >  
> > > -- 
> > > 2.25.1
> > >   
> --
> Thanks,
> 
> weiyufeng
> 
> 

Re: [PATCH] PCI: Add PCI_EXT_CAP_ID_PL_64GT define

[Bjorn Helgaas]

On Thu, Aug 08, 2024 at 10:32:17AM +0800, 412574090@163.com wrote:

You inadvertently trimmed out Ilpo's attribution.  Some hints at
https://subspace.kernel.org/etiquette.html

There should be a line like this:

  > On Tue, Aug 06, 2024 at 05:38:41PM +0300, Ilpo Järvinen wrote:
  ...
  > > These should be in numerical order.

so it's clear who wrote what.

> > On Tue, 6 Aug 2024, 412574090@163.com wrote:
> >
> > > From: weiyufeng <weiyufeng@kylinos.cn>
> > 
> > > PCIe r6.0, sec 7.7.7.1, defines a new 64.0 GT/s PCIe Extended Capability
> > > ID,Add the define for PCI_EXT_CAP_ID_PL_64GT for drivers that will want
> > > this whilst doing Gen6 accesses.
> > > 
> > > Signed-off-by: weiyufeng <weiyufeng@kylinos.cn>
> > > ---
> > >  include/uapi/linux/pci_regs.h | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > > index 94c00996e633..cc875534dae1 100644
> > > --- a/include/uapi/linux/pci_regs.h
> > > +++ b/include/uapi/linux/pci_regs.h
> > > @@ -741,6 +741,7 @@
> > >  #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
> > >  #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
> > >  #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
> > > +#define PCI_EXT_CAP_ID_PL_64GT  0x31    /* Physical Layer 64.0 GT/s */
> > >  #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
> 
> > These should be in numerical order.
> In PCIe r6.0, PCI_EXT_CAP_ID_PL_64GT value is 0x31.

Right.  The #defines just need to be sorted in numerical order
(PCI_EXT_CAP_ID_PL_64GT would be last, after PCI_EXT_CAP_ID_DOE)
because PCI_EXT_CAP_ID_MAX is defined to be the one with the highest
numerical value, and it's hard to find that when they're not sorted.

> > >  #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
> 
> > This was not adapted??
> PCIe r6.0, sec 7.7.7.1 have this definition。

I think Ilpo meant that if we add "#define PCI_EXT_CAP_ID_PL_64GT 0x31",
PCI_EXT_CAP_ID_MAX needs to be updated from PCI_EXT_CAP_ID_DOE to
PCI_EXT_CAP_ID_PL_64GT.

Bjorn