* [PATCH 0/2] RISC-V: Add Zicclsm extension support @ 2024-08-09 16:22 Jesse Taube 2024-08-09 16:22 ` [PATCH 1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube 2024-08-09 16:22 ` [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube 0 siblings, 2 replies; 8+ messages in thread From: Jesse Taube @ 2024-08-09 16:22 UTC (permalink / raw) To: linux-riscv Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Jesse Taube, Charlie Jenkins, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree This set is the first two commits of RISC-V: Detect and report speed of unaligned vector accesses [1] rebased onto palmer/for-next. The rational for adding Zicclsm was related to detecting unaligned vector accesses though this reasoning is gone. I don't see why Zicclsm shouldn't be added which is why I'm sending this set. [1] https://lore.kernel.org/all/20240726163719.1667923-1-jesse@rivosinc.com/ Jesse Taube (2): RISC-V: Add Zicclsm to cpufeature and hwprobe dt-bindings: riscv: Add Zicclsm ISA extension description. Documentation/arch/riscv/hwprobe.rst | 5 +++++ Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 6 files changed, 16 insertions(+) --- base-commit: 2d1f51d8a4b0c3fc0b2b79d4e5b95a6813500092 -- 2.45.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe 2024-08-09 16:22 [PATCH 0/2] RISC-V: Add Zicclsm extension support Jesse Taube @ 2024-08-09 16:22 ` Jesse Taube 2024-08-09 18:49 ` Charlie Jenkins 2024-08-09 16:22 ` [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube 1 sibling, 1 reply; 8+ messages in thread From: Jesse Taube @ 2024-08-09 16:22 UTC (permalink / raw) To: linux-riscv Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Jesse Taube, Charlie Jenkins, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley > Zicclsm Misaligned loads and stores to main memory regions with both > the cacheability and coherence PMAs must be supported. > Note: > This introduces a new extension name for this feature. > This requires misaligned support for all regular load and store > instructions (including scalar and vector) but not AMOs or other > specialized forms of memory access. Even though mandated, misaligned > loads and stores might execute extremely slowly. Standard software > distributions should assume their existence only for correctness, > not for performance. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com> --- V1 -> V2: - Add documentation for Zicclsm - Move Zicclsm to correct location V2 -> V3: - No changes V3 -> V4: - Add definitions to hwprobe.rst V4 -> V5: - No changes V5 -> V6: - No changes V6 -> V7: - No changes V7 -> V8: - Rebase onto 2d1f51d8a4b0 (palmer/for-next) - Change commit description --- Documentation/arch/riscv/hwprobe.rst | 5 +++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 5 files changed, 9 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 3db60a0911df..22c118df520b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -239,6 +239,11 @@ The following keys are defined: ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported as + defined in the RISC-V RVA Profiles Specification. Misaligned support for + all regular load and store instructions (including scalar and vector) but + not AMOs or other specialized forms of memory access. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5a0bd27fd11a..c93d957458f0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -92,6 +92,7 @@ #define RISCV_ISA_EXT_ZCF 83 #define RISCV_ISA_EXT_ZCMOP 84 #define RISCV_ISA_EXT_ZAWRS 85 +#define RISCV_ISA_EXT_ZICCLSM 86 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index b706c8e47b02..a9370968fc9f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -72,6 +72,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 49) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8f20607adb40..2f54d811a9b8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -314,6 +314,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { riscv_ext_zicbom_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 8d1b5c35d2a7..01eea29a56cd 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -107,6 +107,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCB); EXT_KEY(ZCMOP); EXT_KEY(ZICBOZ); + EXT_KEY(ZICCLSM); EXT_KEY(ZICOND); EXT_KEY(ZIHINTNTL); EXT_KEY(ZIHINTPAUSE); -- 2.45.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe 2024-08-09 16:22 ` [PATCH 1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube @ 2024-08-09 18:49 ` Charlie Jenkins 0 siblings, 0 replies; 8+ messages in thread From: Charlie Jenkins @ 2024-08-09 18:49 UTC (permalink / raw) To: Jesse Taube Cc: linux-riscv, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley On Fri, Aug 09, 2024 at 12:22:39PM -0400, Jesse Taube wrote: > > Zicclsm Misaligned loads and stores to main memory regions with both > > the cacheability and coherence PMAs must be supported. > > Note: > > This introduces a new extension name for this feature. > > This requires misaligned support for all regular load and store > > instructions (including scalar and vector) but not AMOs or other > > specialized forms of memory access. Even though mandated, misaligned > > loads and stores might execute extremely slowly. Standard software > > distributions should assume their existence only for correctness, > > not for performance. You left in the > characters. Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Andy Chiu <andy.chiu@sifive.com> > --- > V1 -> V2: > - Add documentation for Zicclsm > - Move Zicclsm to correct location > V2 -> V3: > - No changes > V3 -> V4: > - Add definitions to hwprobe.rst > V4 -> V5: > - No changes > V5 -> V6: > - No changes > V6 -> V7: > - No changes > V7 -> V8: > - Rebase onto 2d1f51d8a4b0 (palmer/for-next) > - Change commit description > --- > Documentation/arch/riscv/hwprobe.rst | 5 +++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > arch/riscv/kernel/sys_hwprobe.c | 1 + > 5 files changed, 9 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 3db60a0911df..22c118df520b 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -239,6 +239,11 @@ The following keys are defined: > ratified in commit 98918c844281 ("Merge pull request #1217 from > riscv/zawrs") of riscv-isa-manual. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported as > + defined in the RISC-V RVA Profiles Specification. Misaligned support for > + all regular load and store instructions (including scalar and vector) but > + not AMOs or other specialized forms of memory access. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 5a0bd27fd11a..c93d957458f0 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -92,6 +92,7 @@ > #define RISCV_ISA_EXT_ZCF 83 > #define RISCV_ISA_EXT_ZCMOP 84 > #define RISCV_ISA_EXT_ZAWRS 85 > +#define RISCV_ISA_EXT_ZICCLSM 86 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index b706c8e47b02..a9370968fc9f 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -72,6 +72,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) > +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 49) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 8f20607adb40..2f54d811a9b8 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -314,6 +314,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > riscv_ext_zicbom_validate), > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, > riscv_ext_zicboz_validate), > + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), > __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 8d1b5c35d2a7..01eea29a56cd 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -107,6 +107,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZCB); > EXT_KEY(ZCMOP); > EXT_KEY(ZICBOZ); > + EXT_KEY(ZICCLSM); > EXT_KEY(ZICOND); > EXT_KEY(ZIHINTNTL); > EXT_KEY(ZIHINTPAUSE); > -- > 2.45.2 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. 2024-08-09 16:22 [PATCH 0/2] RISC-V: Add Zicclsm extension support Jesse Taube 2024-08-09 16:22 ` [PATCH 1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube @ 2024-08-09 16:22 ` Jesse Taube 2024-08-09 18:15 ` Rob Herring 1 sibling, 1 reply; 8+ messages in thread From: Jesse Taube @ 2024-08-09 16:22 UTC (permalink / raw) To: linux-riscv Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Jesse Taube, Charlie Jenkins, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley Add description for Zicclsm ISA extension. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- V1 -> V2: - New patch V2 -> V3: - No changes V3 -> V4: - No changes V4 -> V5: - No changes V5 -> V6: - No changes V6 -> V7: - No changes V7 -> V8: - Rebase onto 2d1f51d8a4b0 (palmer/for-next) --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..d06ee82abcc1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -361,6 +361,13 @@ properties: The standard Zicboz extension for cache-block zeroing as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: zicclsm + description: + The standard Zicclsm extension for misaligned support for all regular + load and store instructions (including scalar and vector) but not AMOs + or other specialized forms of memory access. Defined in the + RISC-V RVA Profiles Specification. + - const: zicntr description: The standard Zicntr extension for base counters and timers, as -- 2.45.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. 2024-08-09 16:22 ` [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube @ 2024-08-09 18:15 ` Rob Herring 2024-08-09 18:56 ` Charlie Jenkins 0 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2024-08-09 18:15 UTC (permalink / raw) To: Jesse Taube Cc: linux-riscv, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Charlie Jenkins, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley On Fri, Aug 09, 2024 at 12:22:40PM -0400, Jesse Taube wrote: > Add description for Zicclsm ISA extension. > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > V1 -> V2: > - New patch > V2 -> V3: > - No changes > V3 -> V4: > - No changes > V4 -> V5: > - No changes > V5 -> V6: > - No changes > V6 -> V7: > - No changes > V7 -> V8: > - Rebase onto 2d1f51d8a4b0 (palmer/for-next) Please also put the version in the subject. '-vN' is the git-send-email option to do it for you. Rob ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. 2024-08-09 18:15 ` Rob Herring @ 2024-08-09 18:56 ` Charlie Jenkins 2024-08-12 15:56 ` Conor Dooley 0 siblings, 1 reply; 8+ messages in thread From: Charlie Jenkins @ 2024-08-09 18:56 UTC (permalink / raw) To: Rob Herring Cc: Jesse Taube, linux-riscv, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley On Fri, Aug 09, 2024 at 12:15:36PM -0600, Rob Herring wrote: > On Fri, Aug 09, 2024 at 12:22:40PM -0400, Jesse Taube wrote: > > Add description for Zicclsm ISA extension. > > > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> > > --- > > V1 -> V2: > > - New patch > > V2 -> V3: > > - No changes > > V3 -> V4: > > - No changes > > V4 -> V5: > > - No changes > > V5 -> V6: > > - No changes > > V6 -> V7: > > - No changes > > V7 -> V8: > > - Rebase onto 2d1f51d8a4b0 (palmer/for-next) > > Please also put the version in the subject. '-vN' is the git-send-email > option to do it for you. > > Rob > These patches were originally part of a different series [1] but are no longer related to that series so I had asked Jesse to spin these off into a different series. These version tags probably should not have been left on here when made into this new series though. - Charlie Link: https://lore.kernel.org/lkml/20240726163719.1667923-1-jesse@rivosinc.com/ [1] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. 2024-08-09 18:56 ` Charlie Jenkins @ 2024-08-12 15:56 ` Conor Dooley 2024-08-12 16:47 ` Jesse Taube 0 siblings, 1 reply; 8+ messages in thread From: Conor Dooley @ 2024-08-12 15:56 UTC (permalink / raw) To: Charlie Jenkins Cc: Rob Herring, Jesse Taube, linux-riscv, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley [-- Attachment #1: Type: text/plain, Size: 1294 bytes --] On Fri, Aug 09, 2024 at 11:56:14AM -0700, Charlie Jenkins wrote: > On Fri, Aug 09, 2024 at 12:15:36PM -0600, Rob Herring wrote: > > On Fri, Aug 09, 2024 at 12:22:40PM -0400, Jesse Taube wrote: > > > Add description for Zicclsm ISA extension. > > > > > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> > > > --- > > > V1 -> V2: > > > - New patch > > > V2 -> V3: > > > - No changes > > > V3 -> V4: > > > - No changes > > > V4 -> V5: > > > - No changes > > > V5 -> V6: > > > - No changes > > > V6 -> V7: > > > - No changes > > > V7 -> V8: > > > - Rebase onto 2d1f51d8a4b0 (palmer/for-next) > > > > Please also put the version in the subject. '-vN' is the git-send-email > > option to do it for you. > > > > Rob > > > > These patches were originally part of a different series [1] but are no > longer related to that series so I had asked Jesse to spin these off into a > different series. These version tags probably should not have been left > on here when made into this new series though. I dunno, I disagree. I think the versioning should continue on being split - especially when there's been tags provided on earlier versions. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. 2024-08-12 15:56 ` Conor Dooley @ 2024-08-12 16:47 ` Jesse Taube 0 siblings, 0 replies; 8+ messages in thread From: Jesse Taube @ 2024-08-12 16:47 UTC (permalink / raw) To: Conor Dooley, Charlie Jenkins Cc: Rob Herring, linux-riscv, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Krzysztof Kozlowski, Clément Léger, Evan Green, Andrew Jones, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner, Costa Shulyupin, Andrew Morton, Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer, Joel Granados, linux-doc, linux-kernel, devicetree, Conor Dooley On 8/12/24 11:56, Conor Dooley wrote: > On Fri, Aug 09, 2024 at 11:56:14AM -0700, Charlie Jenkins wrote: >> On Fri, Aug 09, 2024 at 12:15:36PM -0600, Rob Herring wrote: >>> On Fri, Aug 09, 2024 at 12:22:40PM -0400, Jesse Taube wrote: >>>> Add description for Zicclsm ISA extension. >>>> >>>> Signed-off-by: Jesse Taube <jesse@rivosinc.com> >>>> Acked-by: Conor Dooley <conor.dooley@microchip.com> >> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> >>>> --- >>>> V1 -> V2: >>>> - New patch >>>> V2 -> V3: >>>> - No changes >>>> V3 -> V4: >>>> - No changes >>>> V4 -> V5: >>>> - No changes >>>> V5 -> V6: >>>> - No changes >>>> V6 -> V7: >>>> - No changes >>>> V7 -> V8: >>>> - Rebase onto 2d1f51d8a4b0 (palmer/for-next) >>> >>> Please also put the version in the subject. '-vN' is the git-send-email >>> option to do it for you. >>> >>> Rob >>> >> >> These patches were originally part of a different series [1] but are no >> longer related to that series so I had asked Jesse to spin these off into a >> different series. These version tags probably should not have been left >> on here when made into this new series though. > > I dunno, I disagree. I think the versioning should continue on being > split - especially when there's been tags provided on earlier versions. Good to know I should keep the version number when splinting a set. Thanks, Jesse ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-08-12 16:47 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-08-09 16:22 [PATCH 0/2] RISC-V: Add Zicclsm extension support Jesse Taube 2024-08-09 16:22 ` [PATCH 1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube 2024-08-09 18:49 ` Charlie Jenkins 2024-08-09 16:22 ` [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube 2024-08-09 18:15 ` Rob Herring 2024-08-09 18:56 ` Charlie Jenkins 2024-08-12 15:56 ` Conor Dooley 2024-08-12 16:47 ` Jesse Taube
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