Re: [PATCH v2 25/36] soc: fsl: cpm1: qmc: Re-order probe() operations

Christophe Leroy
2024-08-23T08:11:42Z

Le 08/08/2024 à 09:11, Herve Codina a écrit :
> Current code handles CPM1 version of QMC. In the QUICC Engine (QE)
> version, some operations done at probe() need to be done in a different
> order.
>
> In order to prepare the support for the QE version, changed the sequence
> of operation done at probe():
> - Retrieve the tsa_serial earlier, before initializing resources.
> - Group SCC initialisation and do this initialization when it is really
> needed in the probe() sequence.
>
> Having the QE compatible sequence in the CPM1 version does not lead to
> any issue and works correctly without any regressions.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>

> ---
> drivers/soc/fsl/qe/qmc.c | 54 +++++++++++++++++++---------------------
> 1 file changed, 26 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 85fc86f91806..8dd0f8fc7b08 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -1614,6 +1614,12 @@ static int qmc_probe(struct platform_device *pdev)
> }
> INIT_LIST_HEAD(&qmc->chan_head);
>
> + qmc->tsa_serial = devm_tsa_serial_get_byphandle(qmc->dev, np, "fsl,tsa-serial");
> + if (IS_ERR(qmc->tsa_serial)) {
> + return dev_err_probe(qmc->dev, PTR_ERR(qmc->tsa_serial),
> + "Failed to get TSA serial\n");
> + }
> +
> qmc->scc_regs = devm_platform_ioremap_resource_byname(pdev, "scc_regs");
> if (IS_ERR(qmc->scc_regs))
> return PTR_ERR(qmc->scc_regs);
> @@ -1630,33 +1636,13 @@ static int qmc_probe(struct platform_device *pdev)
> if (IS_ERR(qmc->dpram))
> return PTR_ERR(qmc->dpram);
>
> - qmc->tsa_serial = devm_tsa_serial_get_byphandle(qmc->dev, np, "fsl,tsa-serial");
> - if (IS_ERR(qmc->tsa_serial)) {
> - return dev_err_probe(qmc->dev, PTR_ERR(qmc->tsa_serial),
> - "Failed to get TSA serial\n");
> - }
> -
> - /* Connect the serial (SCC) to TSA */
> - ret = tsa_serial_connect(qmc->tsa_serial);
> - if (ret) {
> - dev_err(qmc->dev, "Failed to connect TSA serial\n");
> - return ret;
> - }
> -
> /* Parse channels informationss */
> ret = qmc_of_parse_chans(qmc, np);
> if (ret)
> - goto err_tsa_serial_disconnect;
> + return ret;
>
> nb_chans = qmc_nb_chans(qmc);
>
> - /* Init GMSR_H and GMSR_L registers */
> - qmc_write32(qmc->scc_regs + SCC_GSMRH,
> - SCC_GSMRH_CDS | SCC_GSMRH_CTSS | SCC_GSMRH_CDP | SCC_GSMRH_CTSP);
> -
> - /* enable QMC mode */
> - qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
> -
> /*
> * Allocate the buffer descriptor table
> * 8 rx and 8 tx descriptors per channel
> @@ -1666,8 +1652,7 @@ static int qmc_probe(struct platform_device *pdev)
> &qmc->bd_dma_addr, GFP_KERNEL);
> if (!qmc->bd_table) {
> dev_err(qmc->dev, "Failed to allocate bd table\n");
> - ret = -ENOMEM;
> - goto err_tsa_serial_disconnect;
> + return -ENOMEM;
> }
> memset(qmc->bd_table, 0, qmc->bd_size);
>
> @@ -1679,8 +1664,7 @@ static int qmc_probe(struct platform_device *pdev)
> &qmc->int_dma_addr, GFP_KERNEL);
> if (!qmc->int_table) {
> dev_err(qmc->dev, "Failed to allocate interrupt table\n");
> - ret = -ENOMEM;
> - goto err_tsa_serial_disconnect;
> + return -ENOMEM;
> }
> memset(qmc->int_table, 0, qmc->int_size);
>
> @@ -1699,18 +1683,32 @@ static int qmc_probe(struct platform_device *pdev)
>
> ret = qmc_init_tsa(qmc);
> if (ret)
> - goto err_tsa_serial_disconnect;
> + return ret;
>
> qmc_write16(qmc->scc_pram + QMC_GBL_QMCSTATE, 0x8000);
>
> ret = qmc_setup_chans(qmc);
> if (ret)
> - goto err_tsa_serial_disconnect;
> + return ret;
>
> /* Init interrupts table */
> ret = qmc_setup_ints(qmc);
> if (ret)
> - goto err_tsa_serial_disconnect;
> + return ret;
> +
> + /* Connect the serial (SCC) to TSA */
> + ret = tsa_serial_connect(qmc->tsa_serial);
> + if (ret) {
> + dev_err(qmc->dev, "Failed to connect TSA serial\n");
> + return ret;
> + }
> +
> + /* Init GMSR_H and GMSR_L registers */
> + qmc_write32(qmc->scc_regs + SCC_GSMRH,
> + SCC_GSMRH_CDS | SCC_GSMRH_CTSS | SCC_GSMRH_CDP | SCC_GSMRH_CTSP);
> +
> + /* enable QMC mode */
> + qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
>
> /* Disable and clear interrupts, set the irq handler */
> qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);