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From: Jacob Pan <jacob.pan@linux.microsoft.com>
To: Yi Liu <yi.l.liu@intel.com>
Cc: Baolu Lu <baolu.lu@linux.intel.com>,
	Tina Zhang <tina.zhang@intel.com>,
	Kevin Tian <kevin.tian@intel.com>, <iommu@lists.linux.dev>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 4/4] iommu/vt-d: Introduce batched cache invalidation
Date: Mon, 19 Aug 2024 08:53:34 -0700	[thread overview]
Message-ID: <20240819085334.247199c3@DESKTOP-0403QTC.> (raw)
In-Reply-To: <03553755-6404-4bb3-badf-5091755f36b7@intel.com>

Hi Yi,

On Mon, 19 Aug 2024 15:58:35 +0800
Yi Liu <yi.l.liu@intel.com> wrote:

> On 2024/8/17 11:28, Baolu Lu wrote:
> > On 2024/8/17 0:38, Jacob Pan wrote:  
> >> On Thu, 15 Aug 2024 14:52:21 +0800
> >> Tina Zhang <tina.zhang@intel.com> wrote:
> >>  
> >>> @@ -270,7 +343,8 @@ static void cache_tag_flush_iotlb(struct
> >>> dmar_domain *domain, struct cache_tag * u64 type =
> >>> DMA_TLB_PSI_FLUSH; if (domain->use_first_level) {
> >>> -        qi_flush_piotlb(iommu, tag->domain_id, tag->pasid,
> >>> addr, pages, ih);
> >>> +        qi_batch_add_piotlb(iommu, tag->domain_id,
> >>> tag->pasid, addr,
> >>> +                    pages, ih, domain->qi_batch);
> >>>           return;
> >>>       }
> >>> @@ -287,7 +361,8 @@ static void cache_tag_flush_iotlb(struct
> >>> dmar_domain *domain, struct cache_tag * }
> >>>       if (ecap_qis(iommu->ecap))
> >>> -        qi_flush_iotlb(iommu, tag->domain_id, addr | ih,
> >>> mask, type);
> >>> +        qi_batch_add_iotlb(iommu, tag->domain_id, addr | ih,
> >>> mask, type,
> >>> +                   domain->qi_batch);  
> >> If I understand this correctly, IOTLB flush maybe deferred until
> >> the batch array is full, right? If so, is there a security gap
> >> where callers think the mapping is gone after the call returns?  
> > No. All related caches are flushed before function return. A domain
> > can have multiple cache tags. Previously, we sent individual cache
> > invalidation requests to hardware. This change combines all
> > necessary invalidation requests into a single batch and raise them
> > to hardware together to make it more efficient.  
> 
> Hi Jacob,
> 
> Do you mean the configuration that iommu.strict==0? :) As the above
> explanation from Baolu, this patch is not for that although it uses
> the term "batched". Also, it would reduce the VMExits that due to the
> IOTLB/DevTLB invalidation a lot in the virtualization environment.
> 
No, I understand this is a different "batch", not for deferred flush.
I am asking why it has to gather QI_MAX_BATCHED_DESC_COUNT before it
does the flush. See my other reply.

Thanks,

Jacob




  reply	other threads:[~2024-08-19 15:53 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-15  6:52 [PATCH v3 0/4] Batch IOTLB/dev-IOTLB invalidation Tina Zhang
2024-08-15  6:52 ` [PATCH v3 1/4] iommu/vt-d: Factor out invalidation descriptor composition Tina Zhang
2024-08-15  6:52 ` [PATCH v3 2/4] iommu/vt-d: Refactor IOTLB and Dev-IOTLB flush for batching Tina Zhang
2024-08-15  6:52 ` [PATCH v3 3/4] iommu/vt-d: Add qi_batch for dmar_domain Tina Zhang
2024-08-15  6:52 ` [PATCH v3 4/4] iommu/vt-d: Introduce batched cache invalidation Tina Zhang
2024-08-16 16:38   ` Jacob Pan
2024-08-17  3:28     ` Baolu Lu
2024-08-19  7:58       ` Yi Liu
2024-08-19 15:53         ` Jacob Pan [this message]
2024-08-19 15:40       ` Jacob Pan
2024-08-20  2:06         ` Baolu Lu
2024-08-20 23:04           ` Jacob Pan
2024-09-02  2:32 ` [PATCH v3 0/4] Batch IOTLB/dev-IOTLB invalidation Baolu Lu

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