From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Frank Li <Frank.Li@nxp.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Boris Brezillon <boris.brezillon@collabora.com>,
Parshuram Thombare <pthombar@cadence.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Boris Brezillon <bbrezillon@kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Conor Culhane <conor.culhane@silvaco.com>,
linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev
Subject: Re: [PATCH v3 09/11] i3c: master: svc: use spinlock_saveirq at svc_i3c_master_ibi_work()
Date: Fri, 23 Aug 2024 18:19:27 +0200 [thread overview]
Message-ID: <20240823181927.7a003c36@xps-13> (raw)
In-Reply-To: <20240819-i3c_fix-v3-9-7d69f7b0a05e@nxp.com>
Hi Frank,
Frank.Li@nxp.com wrote on Mon, 19 Aug 2024 12:02:03 -0400:
> According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5:
>
> The I3C Controller shall hold SCL Low while the Bus is in I3C/I2C Transfer,
low transfer
> ACK/NACK Phase. But maximum stall time is 100us. We have to disable irq and
and/or (I'm not sure) the IRQs
> schedule during whole I3C transaction, otherwise, I3C bus timeout will
prevnet scheduling during the whole the may
timeout.
> happen if any irq or schedule happen during transaction.
>
> Replace mutex with spinlock_saveirq() to make sure finish whole i3c
wrong name to avoid stalling SCL...
> transaction without stall SCL more than 100us.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Yes, 100us is low, and that's why I initially did my best to enforce
auto ack/nack. We cannot make sure this limit will not be crossed, and
when it's the case, we need to handle the consequences.
> ---
> drivers/i3c/master/svc-i3c-master.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index 161ccd824443b..fbb6cef405577 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c
> @@ -432,7 +432,16 @@ static void svc_i3c_master_ibi_work(struct work_struct *work)
> u32 status, val;
> int ret;
>
> - mutex_lock(&master->lock);
Don't you still need this lock for other concurrency reasons?
> + /*
> + * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5:
> + *
> + * The I3C Controller shall hold SCL Low while the Bus is in I3C/I2C Transfer, ACK/NACK
> + * Phase. But maximum stall time is 100us. We have to disable irq and schedule during whole
> + * I3C transaction, otherwise, I3C bus timeout will happen if any irq or schedule happen
> + * between transaction..
> + */
> + guard(spinlock_irqsave)(&master->xferqueue.lock);
> +
> /*
> * IBIWON may be set before SVC_I3C_MCTRL_REQUEST_AUTO_IBI, causing
> * readl_relaxed_poll_timeout() to return immediately. Consequently,
> @@ -452,7 +461,7 @@ static void svc_i3c_master_ibi_work(struct work_struct *work)
> master->regs + SVC_I3C_MCTRL);
>
> /* Wait for IBIWON, should take approximately 100us */
> - ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
> + ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val,
> SVC_I3C_MSTATUS_IBIWON(val), 0, 1000);
This means you lock one CPU for 100us doing nothing every time you send
a frame, that's not possible. Actually the delay was already very small
(could have been set to ~10 maybe) but this is not possible.
> if (ret) {
> dev_err(master->dev, "Timeout when polling for IBIWON\n");
> @@ -525,7 +534,6 @@ static void svc_i3c_master_ibi_work(struct work_struct *work)
>
> reenable_ibis:
> svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
> - mutex_unlock(&master->lock);
> }
>
> static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
>
Thanks,
Miquèl
next prev parent reply other threads:[~2024-08-23 16:19 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-19 16:01 [PATCH v3 00/11] i3c: master: some fix and improvemnt for hotjoin Frank Li
2024-08-19 16:01 ` [PATCH v3 01/11] i3c: master: Remove i3c_dev_disable_ibi_locked(olddev) on device hotjoin Frank Li
2024-08-20 1:34 ` Stanley Chu
2024-08-20 14:45 ` Frank Li
2024-08-23 15:53 ` Miquel Raynal
2024-08-19 16:01 ` [PATCH v3 02/11] i3c: master: Replace hard code 2 with macro I3C_ADDR_SLOT_BITS Frank Li
2024-08-23 15:55 ` Miquel Raynal
2024-08-23 17:57 ` Frank Li
2024-08-26 8:05 ` Miquel Raynal
2024-08-19 16:01 ` [PATCH v3 03/11] i3c: master: Extend address status bit to 4 and add I3C_ADDR_SLOT_EXT_INIT Frank Li
2024-08-23 16:04 ` Miquel Raynal
2024-08-23 17:55 ` Frank Li
2024-08-26 8:04 ` Miquel Raynal
2024-08-26 15:56 ` Frank Li
2024-08-26 16:49 ` Miquel Raynal
2024-08-26 18:55 ` Frank Li
2024-09-02 14:12 ` Miquel Raynal
2024-09-02 18:20 ` Frank Li
2024-09-03 13:00 ` Miquel Raynal
2024-09-03 15:06 ` Frank Li
2024-09-09 20:01 ` Frank Li
2024-09-16 15:14 ` Frank Li
2024-08-19 16:01 ` [PATCH v3 04/11] i3c: master: Fix dynamic address leak when 'assigned-address' is present Frank Li
2024-08-19 16:01 ` [PATCH v3 05/11] i3c: master: Fix miss free init_dyn_addr at i3c_master_put_i3c_addrs() Frank Li
2024-08-23 16:07 ` Miquel Raynal
2024-08-19 16:02 ` [PATCH v3 06/11] i3c: master: svc: use repeat start when IBI WIN happens Frank Li
2024-08-23 16:09 ` Miquel Raynal
2024-08-19 16:02 ` [PATCH v3 07/11] i3c: master: svc: manually emit NACK/ACK for hotjoin Frank Li
2024-08-23 16:10 ` Miquel Raynal
2024-08-19 16:02 ` [PATCH v3 08/11] i3c: master: svc: need check IBIWON for dynamtica address assign Frank Li
2024-08-23 16:12 ` Miquel Raynal
2024-08-19 16:02 ` [PATCH v3 09/11] i3c: master: svc: use spinlock_saveirq at svc_i3c_master_ibi_work() Frank Li
2024-08-23 16:19 ` Miquel Raynal [this message]
2024-08-23 16:53 ` Frank Li
2024-08-19 16:02 ` [PATCH v3 10/11] i3c: master: svc: wait for Manual ACK/NACK Done before next step Frank Li
2024-08-23 16:22 ` Miquel Raynal
2024-08-23 16:45 ` Frank Li
2024-08-19 16:02 ` [PATCH v3 11/11] i3c: master: svc: fix possible assignment of the same address to two devices Frank Li
2024-08-23 16:24 ` Miquel Raynal
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