From: Jason Gunthorpe <jgg@nvidia.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
joro@8bytes.org, robin.murphy@arm.com, vasant.hegde@amd.com,
ubizjak@gmail.com, jon.grimm@amd.com, santosh.shukla@amd.com,
pandoh@google.com, kumaranand@google.com
Subject: Re: [PATCH v2 5/5] iommu/amd: Use 128-bit cmpxchg in set_dte_irq_entry()
Date: Thu, 29 Aug 2024 16:40:46 -0300 [thread overview]
Message-ID: <20240829194046.GL3773488@nvidia.com> (raw)
In-Reply-To: <20240829180726.5022-6-suravee.suthikulpanit@amd.com>
On Thu, Aug 29, 2024 at 06:07:26PM +0000, Suravee Suthikulpanit wrote:
> Interrupt-remapping-related fields are in the top 128-bit of the Device
> Table Entry (DTE), which should be updated using 128-bit write based on the
> AMD I/O Virtualization Techonology (IOMMU) Specification.
>
> Therefore, modify set_dte_irq_entry() to use 128-bit cmpxchg. Also, use
> struct dev_data->dte_sem to synchronize DTE access.
>
> Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
> drivers/iommu/amd/iommu.c | 25 ++++++++++++++++---------
> 1 file changed, 16 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index a24986c2478b..4eb53bd40487 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -3020,17 +3020,24 @@ static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid)
> static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid,
> struct irq_remap_table *table)
> {
> - u64 dte;
> - struct dev_table_entry *dev_table = get_dev_table(iommu);
> + u128 new, old;
> + struct dev_table_entry *dte = &get_dev_table(iommu)[devid];
> + struct iommu_dev_data *dev_data = search_dev_data(iommu, devid);
> +
> + if (dev_data)
> + down_write(&dev_data->dte_sem);
> +
> + old = new = dte->data128[1];
> + new &= ~DTE_IRQ_PHYS_ADDR_MASK;
> + new |= iommu_virt_to_phys(table->table);
> + new |= DTE_IRQ_REMAP_INTCTL;
> + new |= DTE_INTTABLEN;
> + new |= DTE_IRQ_REMAP_ENABLE;
>
> - dte = dev_table[devid].data[2];
> - dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
> - dte |= iommu_virt_to_phys(table->table);
> - dte |= DTE_IRQ_REMAP_INTCTL;
> - dte |= DTE_INTTABLEN;
> - dte |= DTE_IRQ_REMAP_ENABLE;
> + WARN_ON(!try_cmpxchg128(&dte->data128[1], &old, new));
This probably doesn't need cmpxchg because it is only touching 64 bit
quanta [2], just a lock is good enough and avoids the "what to do if
cmpxchg fails" question.
> - dev_table[devid].data[2] = dte;
But this should be
WRITE_ONCE(dev_table[devid].data[2], dte);
Beaucse it is writing to memory read back by HW.
Required for all the DTE touches everywhere.
Jason
next prev parent reply other threads:[~2024-08-29 19:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 18:07 [PATCH v2 0/5] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suravee Suthikulpanit
2024-08-29 18:07 ` [PATCH v2 1/5] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Suravee Suthikulpanit
2024-08-29 18:07 ` [PATCH v2 2/5] iommu/amd: Introduce rw_semaphore for Device Table Entry (DTE) Suravee Suthikulpanit
2024-08-29 19:34 ` Jason Gunthorpe
2024-09-05 6:20 ` Suthikulpanit, Suravee
2024-09-05 12:15 ` Jason Gunthorpe
2024-08-29 18:07 ` [PATCH v2 3/5] iommu/amd: Introduce helper functions to access and update 256-bit DTE Suravee Suthikulpanit
2024-08-29 19:28 ` Jason Gunthorpe
2024-09-05 17:54 ` Suthikulpanit, Suravee
2024-09-05 18:21 ` Jason Gunthorpe
2024-09-06 14:08 ` Suthikulpanit, Suravee
2024-09-06 16:01 ` Jason Gunthorpe
2024-08-29 18:07 ` [PATCH v2 4/5] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Suravee Suthikulpanit
2024-08-29 18:07 ` [PATCH v2 5/5] iommu/amd: Use 128-bit cmpxchg in set_dte_irq_entry() Suravee Suthikulpanit
2024-08-29 19:40 ` Jason Gunthorpe [this message]
2024-09-05 5:32 ` Suthikulpanit, Suravee
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