Re: [PATCH v3 07/12] arm64: dts: renesas: r9a08g045: Add VBATTB node

claudiu beznea
2024-09-04T12:17:34Z

Hi, Stephen,

On 03.09.2024 22:48, Stephen Boyd wrote:
> Quoting Claudiu (2024-08-30 06:02:13)
>> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
>> index 067a26a66c24..247fa80a4f53 100644
>> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
>> @@ -160,6 +160,18 @@ i2c3: i2c@10090c00 {
>> status = "disabled";
>> };
>>
>> + vbattb: vbattb@1005c000 {
>> + compatible = "renesas,r9a08g045-vbattb";
>> + reg = <0 0x1005c000 0 0x1000>;
>> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
>> + clock-names = "bclk", "rtx";
>> + #clock-cells = <1>;
>> + power-domains = <&cpg>;
>> + resets = <&cpg R9A08G045_VBAT_BRESETN>;
>> + status = "disabled";
>> + };
>> +
>> cpg: clock-controller@11010000 {
>> compatible = "renesas,r9a08g045-cpg";
>> reg = <0 0x11010000 0 0x10000>;
>> @@ -425,4 +437,11 @@ timer {
>> interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
>> "hyp-virt";
>> };
>> +
>> + vbattb_xtal: vbattb-xtal {
>
> The node name should be something like clock-<frequency> but if the
> frequency is different per-board then I don't know what should happen
> here.

The frequency should be always around 32768 Hz but not necessarily exactly
32768 Hz. It depends on what is installed on the board, indeed. RTC can do
time error adjustments based on the variations around 32768 Hz.

> Can you leave the vbattb_xtal phandle up above and then require
> the node to be defined in the board with the proper frequency after the
> dash?

Is it OK for you something like this (applied on top of this series)?

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index f31ec08a1e1d..60679211dc48 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -181,7 +181,8 @@ vbattb: clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0 0x1005c000 0 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>,
<&vbattb_xtal>;
+ /* rtx clock must be overridden by the board. */
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <0>;
clock-names = "bclk", "rtx";
#clock-cells = <1>;
power-domains = <&cpg>;
@@ -454,11 +455,4 @@ timer {
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
-
- vbattb_xtal: vbattb-xtal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 95b79a03d3d5..46cce0d48ddc 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -47,6 +47,12 @@ chosen {
stdout-path = "serial0:115200n8";
};

+ vbattb_xtal: clock-32768 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
memory@48000000 {
device_type = "memory";
/* First 128MB is reserved for secure area. */
@@ -351,14 +357,11 @@ &rtc {
};

&vbattb {
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
renesas,vbattb-load-nanofarads = <12500>;
status = "okay";
};

-&vbattb_xtal {
- clock-frequency = <32768>;
-};
-
&wdt0 {
timeout-sec = <60>;
status = "okay";

Thank you for your review,
Claudiu Beznea

>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + /* This value must be overridden by the board. */
>> + clock-frequency = <0>;