RE: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB

Biju Das
2024-09-03T07:25:20Z

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, September 3, 2024 8:23 AM
> Subject: Re: [PATCH v3 01/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
>
> Hi Biju,
>
> On Tue, Sep 3, 2024 at 8:58 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Claudiu <claudiu.beznea@tuxon.dev>
> > > Sent: Friday, August 30, 2024 2:02 PM
> > > Subject: [PATCH v3 01/12] dt-bindings: clock:
> > > renesas,r9a08g045-vbattb: Document VBATTB
> > >
> > > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > >
> > > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> > > the tamper detector and a small general usage memory of 128B. Add documentation for it.
> > >
> > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbat
> > > +++ tb.yaml
> > > + power-domains:
> > > + maxItems: 1
> >
> > Not sure, you need to document "PD_VBATT" power domain as per Table
> > 41.2, this LSI supports 3 power domains(PD_ISOVCC, PD_VCC, PD_VBATT)
> >
> > Power Mode PD_ISOVCC PD_VCC PD_VBATT
> > ALL_ON ON ON ON
> > AWO OFF ON ON
> > VBATT OFF OFF ON
> > ALL_OFF OFF OFF OFF
> >
> > PD_VBATT domain is the area where the RTC/backup register is located,
> > works on battery power when the power of PD_VCC and PD_ISOVCC domain are turned off.
>
> AFAIU, PD_VBATT cannot be controlled by the user, and is just on if main or battery power is supplied.
> So I don't think there is a need to describe it in DT.

OK, Just thought since DT is describing hardware, better to document this.

I am not an expert, So I agree with you.

Cheers,
Biju