[PATCH v2 0/4] Add Aspeed G7 gpio support

Billy Tsai
2024-08-30T03:40:53Z

The Aspeed 7th generation SoC features two GPIO controllers: one with 12
GPIO pins and another with 216 GPIO pins. The main difference from the
previous generation is that the control logic has been updated to support
per-pin control, allowing each pin to have its own 32-bit register for
configuring value, direction, interrupt type, and more.
This patch serial also add low-level operations (llops) to abstract the
register access for GPIO registers and the coprocessor request/release in
gpio-aspeed.c making it easier to extend the driver to support different
hardware register layouts.

Changes since v1:
- Merge the gpio-aspeed-g7.c into the gpio-aspeed.c.
- Create the llops in gpio-aspeed.c for flexibility.

Billy Tsai (4):
dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700
gpio: aspeed: Remove the name for bank array
gpio: aspeed: Create llops to handle hardware access
gpio: aspeed: Support G7 Aspeed gpio controller

.../bindings/gpio/aspeed,ast2400-gpio.yaml | 46 +-
drivers/gpio/gpio-aspeed.c | 442 ++++++++++--------
2 files changed, 303 insertions(+), 185 deletions(-)

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2.25.1