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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7d22e7821cesm6112899a12.55.2024.09.01.09.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Sep 2024 09:39:12 -0700 (PDT) Date: Mon, 2 Sep 2024 01:39:10 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Prudhvi Yarlagadda Cc: jingoohan1@gmail.com, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, robh@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_mrana@quicinc.com Subject: Re: [PATCH v4] PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region Message-ID: <20240901163910.GD235729@rocinante> References: <20240814220338.1969668-1-quic_pyarlaga@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240814220338.1969668-1-quic_pyarlaga@quicinc.com> Hello, > PARF hardware block which is a wrapper on top of DWC PCIe controller > mirrors the DBI and ATU register space. It uses PARF_SLV_ADDR_SPACE_SIZE > register to get the size of the memory block to be mirrored and uses > PARF_DBI_BASE_ADDR, PARF_ATU_BASE_ADDR registers to determine the base > address of DBI and ATU space inside the memory block that is being > mirrored. > > When a memory region which is located above the SLV_ADDR_SPACE_SIZE > boundary is used for BAR region then there could be an overlap of DBI and > ATU address space that is getting mirrored and the BAR region. This > results in DBI and ATU address space contents getting updated when a PCIe > function driver tries updating the BAR/MMIO memory region. Reference > memory map of the PCIe memory region with DBI and ATU address space > overlapping BAR region is as below. > > |---------------| > | | > | | > ------- --------|---------------| > | | |---------------| > | | | DBI | > | | |---------------|---->DBI_BASE_ADDR > | | | | > | | | | > | PCIe | |---->2*SLV_ADDR_SPACE_SIZE > | BAR/MMIO|---------------| > | Region | ATU | > | | |---------------|---->ATU_BASE_ADDR > | | | | > PCIe | |---------------| > Memory | | DBI | > Region | |---------------|---->DBI_BASE_ADDR > | | | | > | --------| | > | | |---->SLV_ADDR_SPACE_SIZE > | |---------------| > | | ATU | > | |---------------|---->ATU_BASE_ADDR > | | | > | |---------------| > | | DBI | > | |---------------|---->DBI_BASE_ADDR > | | | > | | | > ----------------|---------------| > | | > | | > | | > |---------------| > > Currently memory region beyond the SLV_ADDR_SPACE_SIZE boundary is not > used for BAR region which is why the above mentioned issue is not > encountered. This issue is discovered as part of internal testing when we > tried moving the BAR region beyond the SLV_ADDR_SPACE_SIZE boundary. Hence > we are trying to fix this. > > As PARF hardware block mirrors DBI and ATU register space after every > PARF_SLV_ADDR_SPACE_SIZE (default 0x1000000) boundary multiple, program > maximum possible size to this register by writing 0x80000000 to it(it > considers only powers of 2 as values) to avoid mirroring DBI and ATU to > BAR/MMIO region. Write the physical base address of DBI and ATU register > blocks to PARF_DBI_BASE_ADDR (default 0x0) and PARF_ATU_BASE_ADDR (default > 0x1000) respectively to make sure DBI and ATU blocks are at expected > memory locations. > > The register offsets PARF_DBI_BASE_ADDR_V2, PARF_SLV_ADDR_SPACE_SIZE_V2 > and PARF_ATU_BASE_ADDR are applicable for platforms that use Qcom IP > rev 1.9.0, 2.7.0 and 2.9.0. PARF_DBI_BASE_ADDR_V2 and > PARF_SLV_ADDR_SPACE_SIZE_V2 are applicable for Qcom IP rev 2.3.3. > PARF_DBI_BASE_ADDR and PARF_SLV_ADDR_SPACE_SIZE are applicable for Qcom > IP rev 1.0.0, 2.3.2 and 2.4.0. Update init()/post_init() functions of the > respective Qcom IP versions to program applicable PARF_DBI_BASE_ADDR, > PARF_SLV_ADDR_SPACE_SIZE and PARF_ATU_BASE_ADDR register offsets. Update > the SLV_ADDR_SPACE_SZ macro to 0x80000000 to set highest bit in > PARF_SLV_ADDR_SPACE_SIZE register. > > Cache DBI and iATU physical addresses in 'struct dw_pcie' so that > pcie_qcom.c driver can program these addresses in the PARF_DBI_BASE_ADDR > and PARF_ATU_BASE_ADDR registers. Applied to controller/qcom, thank you! [1/1] PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region https://git.kernel.org/pci/pci/c/10ba0854c5e6 Krzysztof