From: Bjorn Helgaas <helgaas@kernel.org>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: "Gary Li" <Gary.Li@amd.com>,
"Mario Limonciello" <superm1@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Mathias Nyman" <mathias.nyman@intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"open list : PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
"open list" <linux-kernel@vger.kernel.org>,
"open list : USB XHCI DRIVER" <linux-usb@vger.kernel.org>,
"Daniel Drake" <drake@endlessos.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: Re: [PATCH v5 2/5] PCI: Check PCI_PM_CTRL instead of PCI_COMMAND in pci_dev_wait()
Date: Tue, 3 Sep 2024 13:25:09 -0500 [thread overview]
Message-ID: <20240903182509.GA260253@bhelgaas> (raw)
In-Reply-To: <bdc99602-7bb2-4026-8122-e92f894aca09@amd.com>
On Tue, Sep 03, 2024 at 12:31:00PM -0500, Mario Limonciello wrote:
> On 9/3/2024 12:11, Bjorn Helgaas wrote:
> ...
> > 8) The USB4 stack sees the device and assumes it is in D0, but it
> > seems to still be in D3cold. What is this based on? Is there a
> > config read that returns ~0 data when it shouldn't?
>
> Yes there is. From earlier in the thread I have a [log] I shared.
>
> The message emitted is from ring_interrupt_active():
>
> "thunderbolt 0000:e5:00.5: interrupt for TX ring 0 is already enabled"
Right, that's in the cover letter, but I can't tell from this what the
ioread32(ring->nhi->iobase + reg) returned. It looks like this is an
MMIO read of BAR 0, not a config read.
> [log] https://gist.github.com/superm1/cb407766ab15f42f12a6fe9d1196f6fc
next prev parent reply other threads:[~2024-09-03 18:25 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-23 15:40 [PATCH v5 0/5] Verify devices transition from D3cold to D0 Mario Limonciello
2024-08-23 15:40 ` [PATCH v5 1/5] PCI: Use an enum for reset type in pci_dev_wait() Mario Limonciello
2024-08-23 15:40 ` [PATCH v5 2/5] PCI: Check PCI_PM_CTRL instead of PCI_COMMAND " Mario Limonciello
2024-08-23 19:54 ` Bjorn Helgaas
2024-08-26 19:16 ` Mario Limonciello
2024-08-27 17:43 ` Mario Limonciello
2024-08-27 19:44 ` Bjorn Helgaas
2024-08-30 0:01 ` Bjorn Helgaas
2024-09-03 16:29 ` Mario Limonciello
2024-09-03 17:11 ` Bjorn Helgaas
2024-09-03 17:31 ` Mario Limonciello
2024-09-03 18:25 ` Bjorn Helgaas [this message]
2024-09-03 18:32 ` Mario Limonciello
2024-09-03 21:32 ` Bjorn Helgaas
2024-09-04 12:05 ` Mika Westerberg
2024-09-04 15:24 ` Mario Limonciello
2024-09-05 9:33 ` Mika Westerberg
2024-09-09 20:40 ` Mario Limonciello
2024-09-10 9:13 ` Mika Westerberg
2024-09-13 4:12 ` Mario Limonciello
2024-09-13 4:58 ` Mika Westerberg
2024-09-13 7:23 ` Mika Westerberg
2024-09-13 20:56 ` Mario Limonciello
2024-09-15 7:07 ` Mika Westerberg
2024-08-23 15:40 ` [PATCH v5 3/5] PCI: Verify functions currently in D3cold have entered D0 Mario Limonciello
2024-08-23 15:40 ` [PATCH v5 4/5] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays Mario Limonciello
2024-08-23 15:40 ` [PATCH v5 5/5] PCI: Drop Radeon quirk for Macbook Pro 8.2 Mario Limonciello
2024-12-04 17:30 ` [PATCH v5 0/5] Verify devices transition from D3cold to D0 Mario Limonciello
2024-12-04 23:45 ` Bjorn Helgaas
2024-12-05 3:44 ` Mario Limonciello
2024-12-05 18:12 ` Bjorn Helgaas
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