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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Johan Hovold <johan@kernel.org>
Cc: "Richard Zhu" <hongxing.zhu@nxp.com>,
	"Lucas Stach" <l.stach@pengutronix.de>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Shawn Guo" <shawnguo@kernel.org>,
	"Sascha Hauer" <s.hauer@pengutronix.de>,
	"Pengutronix Kernel Team" <kernel@pengutronix.de>,
	"Fabio Estevam" <festevam@gmail.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Chuanhua Lei" <lchuanhua@maxlinear.com>,
	"Marek Vasut" <marek.vasut+renesas@gmail.com>,
	"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	imx@lists.linux.dev, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	abel.vesa@linaro.org, johan+linaro@kernel.org,
	"Shashank Babu Chinta Venkata" <quic_schintav@quicinc.com>
Subject: Re: [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s
Date: Thu, 5 Sep 2024 20:57:42 +0530	[thread overview]
Message-ID: <20240905152742.4llkcjvvu3klmo6j@thinkpad> (raw)
In-Reply-To: <ZtgqvXGgp2sWNg5O@hovoldconsulting.com>

On Wed, Sep 04, 2024 at 11:39:09AM +0200, Johan Hovold wrote:
> On Wed, Sep 04, 2024 at 12:41:59PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > From: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> > 
> > During high data transmission rates such as 16.0 GT/s, there is an
> > increased risk of signal loss due to poor channel quality and interference.
> > This can impact receiver's ability to capture signals accurately. Hence,
> > signal compensation is achieved through appropriate lane equalization
> > settings at both transmitter and receiver. This will result in increased
> > PCIe signal strength.
> > 
> > Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > [mani: dropped the code refactoring and minor changes]
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

[...]

> > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h
> > new file mode 100644
> > index 000000000000..259e04b7bdf9
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h
> > @@ -0,0 +1,8 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> > + */
> > +
> > +#include "pcie-designware.h"
> 
> You only need a forward declaration:
> 
> 	struct dw_pcie;
> 
> > +
> > +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
> 
> Compile guard still missing.
> 

Perhaps we can just get rid of the Kconfig entry and build it by default for
both RC and EP drivers? I don't see a value in building it as a separate module.
And we may also move more common code in the future.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

  parent reply	other threads:[~2024-09-05 15:27 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-04  7:11 [PATCH v6 0/4] PCI: qcom: Add 16.0 GT/s equalization and margining settings Manivannan Sadhasivam via B4 Relay
2024-09-04  7:11 ` [PATCH v6 1/4] PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed' Manivannan Sadhasivam via B4 Relay
2024-09-04  9:21   ` Johan Hovold
2024-09-04 15:58   ` Frank Li
2024-09-04 16:12     ` Manivannan Sadhasivam
2024-09-05  8:36   ` kernel test robot
2024-09-05 16:11   ` kernel test robot
2024-09-04  7:11 ` [PATCH v6 2/4] PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed Manivannan Sadhasivam via B4 Relay
2024-09-04  9:30   ` Johan Hovold
2024-09-04 15:49     ` Manivannan Sadhasivam
2024-09-05  6:45       ` Johan Hovold
2024-09-04 16:01   ` Frank Li
2024-09-04  7:11 ` [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s Manivannan Sadhasivam via B4 Relay
2024-09-04  9:39   ` Johan Hovold
2024-09-04 15:52     ` Manivannan Sadhasivam
2024-09-04 20:46       ` Shashank Babu Chinta Venkata
2024-09-05  6:50         ` Johan Hovold
2024-09-05 15:27     ` Manivannan Sadhasivam [this message]
2024-09-05 16:27       ` Johan Hovold
2024-09-05 17:34         ` Manivannan Sadhasivam
2024-09-06  6:49           ` Johan Hovold
2024-09-10 17:00             ` Manivannan Sadhasivam
2024-09-04  7:12 ` [PATCH v6 4/4] PCI: qcom: Add RX margining " Manivannan Sadhasivam via B4 Relay
2024-09-04  9:53   ` Johan Hovold
2024-09-04 16:04     ` Manivannan Sadhasivam
2024-09-04 20:48       ` Shashank Babu Chinta Venkata
2024-09-05  7:00         ` Johan Hovold
2024-09-04  9:56 ` [PATCH v6 0/4] PCI: qcom: Add 16.0 GT/s equalization and margining settings Johan Hovold

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