From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6466F14F9F3 for ; Sun, 8 Sep 2024 09:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725788681; cv=none; b=TLAQomfCRAabGI266Sy5xSx/6SFCLJOfU9F4cMZ4lzlLRZENTG+KpypvSrnDGqaY7sRUJNIf/+5/S8goBMOIh7UCe8mR0+6eHIcwQhZunkU3SxzNUBWZkEWg0LC1mmNzNRewYtiE7cUNSXDvLJ+VJ8yI91Jl70pXG2ql14B3mMQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725788681; c=relaxed/simple; bh=vKLv1GOo4aYkB4kll5HRjSGT3siGe21Lr9YlkxhxizA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f3awYjPKnnFR+Slfgp9jDy93WdY1bDdOIti4bDtUyBBYNZm4bPrjmpjee8+wb5Er3GLZAn+VbPO4d3IOaUW1CUmxM8Qzvqqg2kC56Qt6AGoQjSL/xaE4W2ojJzaTAdps5WCDAg1IvGlc5uyGSZdXSwGgLcnftv9wDEXFtmzvcuQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=NAfAgPyV; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="NAfAgPyV" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1725788677; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uiYc0ofxBMVNQjJyGCCIMKHh3G8xIVIFWpF9t4WnSaM=; b=NAfAgPyVk/vLqttARfuiWpFX2GVWYVwq5HAbmGvMqCaeqcV96w/Zg0u0ntPY9jkmTWiy0e A8NHKqx+xrvctx36bAufni8TgnUDUVc3zcoM4m6StAcEurqCS2lP5z5tvyJQcVShvtF/gR ySWlftwzZ48mzdkKZnJsfJIFq8zGYH0= From: Sui Jingfeng To: Lucas Stach Cc: Christian Gmeiner , Russell King , dri-devel@lists.freedesktop.org, etnaviv@lists.freedesktop.org, linux-kernel@vger.kernel.org, Sui Jingfeng Subject: [PATCH v15 07/19] drm/etnaviv: Add a dedicated helper function to get various clocks Date: Sun, 8 Sep 2024 17:43:45 +0800 Message-ID: <20240908094357.291862-8-sui.jingfeng@linux.dev> In-Reply-To: <20240908094357.291862-1-sui.jingfeng@linux.dev> References: <20240908094357.291862-1-sui.jingfeng@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Because the current implementation is DT-based, this only works when the host platform has the DT support. The problem is that some host platforms does not provide DT-based clocks drivers, as a result, the driver rage quit. PLL hardwares are typically provided by the host platform, which is part of the entire clock tree. The PLL hardware provide clock pulse to the GPU core, but it's not belong to the GPU corei itself. PLL registers can be manipulated directly by the device driver. Hence, it may need dedicated clock driver. Add a the etnaviv_gpu_clk_get() function to group similar code blocks, which make it easier to call this function on the platform where it works. Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 53 ++++++++++++++++----------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 4599dd995e11..eca6a06e9ade 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1609,6 +1609,35 @@ static irqreturn_t irq_handler(int irq, void *data) return ret; } +static int etnaviv_gpu_clk_get(struct etnaviv_gpu *gpu) +{ + struct device *dev = gpu->dev; + + gpu->clk_reg = devm_clk_get_optional(dev, "reg"); + DBG("clk_reg: %p", gpu->clk_reg); + if (IS_ERR(gpu->clk_reg)) + return PTR_ERR(gpu->clk_reg); + + gpu->clk_bus = devm_clk_get_optional(dev, "bus"); + DBG("clk_bus: %p", gpu->clk_bus); + if (IS_ERR(gpu->clk_bus)) + return PTR_ERR(gpu->clk_bus); + + gpu->clk_core = devm_clk_get(dev, "core"); + DBG("clk_core: %p", gpu->clk_core); + if (IS_ERR(gpu->clk_core)) + return PTR_ERR(gpu->clk_core); + gpu->base_rate_core = clk_get_rate(gpu->clk_core); + + gpu->clk_shader = devm_clk_get_optional(dev, "shader"); + DBG("clk_shader: %p", gpu->clk_shader); + if (IS_ERR(gpu->clk_shader)) + return PTR_ERR(gpu->clk_shader); + gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); + + return 0; +} + static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) { int ret; @@ -1884,27 +1913,9 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) } /* Get Clocks: */ - gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); - DBG("clk_reg: %p", gpu->clk_reg); - if (IS_ERR(gpu->clk_reg)) - return PTR_ERR(gpu->clk_reg); - - gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); - DBG("clk_bus: %p", gpu->clk_bus); - if (IS_ERR(gpu->clk_bus)) - return PTR_ERR(gpu->clk_bus); - - gpu->clk_core = devm_clk_get(&pdev->dev, "core"); - DBG("clk_core: %p", gpu->clk_core); - if (IS_ERR(gpu->clk_core)) - return PTR_ERR(gpu->clk_core); - gpu->base_rate_core = clk_get_rate(gpu->clk_core); - - gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); - DBG("clk_shader: %p", gpu->clk_shader); - if (IS_ERR(gpu->clk_shader)) - return PTR_ERR(gpu->clk_shader); - gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); + err = etnaviv_gpu_clk_get(gpu); + if (err) + return err; /* TODO: figure out max mapped size */ dev_set_drvdata(dev, gpu); -- 2.43.0