From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B342D1B78F3; Wed, 25 Sep 2024 11:42:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727264549; cv=none; b=siIfoE7YOLvTmIFBYFkNZV6f2ZT5cPkQknY7L6DfNbGdilg/a3L9aYuvgAMFunSvFtzN3dZL3V25lUEqaNqtUSG4M15zgXR2tbF24IefA/KCA9BCYZ4GA83Q9fWsHfazkwtx2NvFKAobLf6FVZjl6nOdL9wCg4RhG1N3HIIqmLQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727264549; c=relaxed/simple; bh=k4M4oCPrSASF+1TmGgx+cteJbKnwOS1p/HkflnkblY0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bRj711dU1xSu7EJILWZu0aXhxis4OXekeKrLfELjiiS3wEAxNXj4vxx/DivQW0nGlno1k9PWhCnCEp7oxXIwFF9TFh/vNhSkf9VkHyDAg5ut5ogQbIid+bxocYWTIEiFmGjiGo620FaDwPXaeeL4noyoO5slP1P6UP4ijfwQjVg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cW6yb2Pw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cW6yb2Pw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 429C5C4CEC3; Wed, 25 Sep 2024 11:42:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727264549; bh=k4M4oCPrSASF+1TmGgx+cteJbKnwOS1p/HkflnkblY0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cW6yb2PwyRCywxr0kyhm2lWNCBEuxQjkxA5hVREKgJT7xwgejDKlG8JdK5dEVwj1W s9AEHCq9yIoSTiyRBmcQJb56TvcbcDdq+w3phXNtYuG7UWWiHxuaCrYlyEBPyAhiRj M0laWb+BPS+Qsr1EDALY5dEQsSUBGKTyzUrbliJQ6dizMzfwGyPlRIt2CO33N9G10Q PG4jFam+AMg507RtHcJMda1vbaSu8U9g+1nEv19eP7tfYb/A7t4GOrG7RLXiLoY68r pprrQ4PjErOlT5tNifzAXkP75dof5lJ1dCNfC+ykSNx5TPWiHY8Zc23jW5pkvg3T+U Qm7N2eLRem9eQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Konrad Dybcio , Sumit Semwal , Will Deacon , Sasha Levin , robdclark@gmail.com, joro@8bytes.org, iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.11 121/244] iommu/arm-smmu-qcom: Work around SDM845 Adreno SMMU w/ 16K pages Date: Wed, 25 Sep 2024 07:25:42 -0400 Message-ID: <20240925113641.1297102-121-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240925113641.1297102-1-sashal@kernel.org> References: <20240925113641.1297102-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.11 Content-Transfer-Encoding: 8bit From: Konrad Dybcio [ Upstream commit 2d42d3ba443706c9164fa0bef4e5fd1c36bc1bd9 ] SDM845's Adreno SMMU is unique in that it actually advertizes support for 16K (and 32M) pages, which doesn't hold for newer SoCs. This however, seems either broken in the hardware implementation, the hypervisor middleware that abstracts the SMMU, or there's a bug in the Linux kernel somewhere down the line that nobody managed to track down. Booting SDM845 with 16K page sizes and drm/msm results in: *** gpu fault: ttbr0=0000000000000000 iova=000100000000c000 dir=READ type=TRANSLATION source=CP (0,0,0,0) right after loading the firmware. The GPU then starts spitting out illegal intstruction errors, as it's quite obvious that it got a bogus pointer. Moreover, it seems like this issue also concerns other implementations of SMMUv2 on Qualcomm SoCs, such as the one on SC7180. Hide 16K support on such instances to work around this. Reported-by: Sumit Semwal Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240824-topic-845_gpu_smmu-v2-1-a302b8acc052@quicinc.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b981ff25a983d..087fb4f6f4d3d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -345,6 +345,14 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) return 0; } +static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu) +{ + /* Support for 16K pages is advertised on some SoCs, but it doesn't seem to work */ + smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K; + + return 0; +} + static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) { struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; @@ -443,6 +451,7 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = { static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { .init_context = qcom_adreno_smmu_init_context, + .cfg_probe = qcom_adreno_smmuv2_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, -- 2.43.0