From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03E722169A; Wed, 25 Sep 2024 12:15:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727266510; cv=none; b=WGoDFjAKBOvwSuvpHoN/HVrU2DRW3Ou8cfdNCEpe6GeDTS5XRJkUnva0q46Cc1YAlMElW/aA8yDlnCDmiQN9OMr95WiGgrT/t6Od1ALWmWmY7KufHyaICcLlsjnMDPey4QU5pRaazucyA4nm/E/biL33EcOYmvWZrJHzNdOjeEg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727266510; c=relaxed/simple; bh=RjfI/WLDaDkKY3bNpnRvp6mIPeVCIol/nkLfahx/6R8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bMrJ3fgBqHBTU10G/cUCFxDm9kBi+a85ChmLDGz6xiKeOFCVsw3mb+NrWlbmOP5qA1wN/wl7BcRuHhqTklpDJgK44HcNoAF968JDnXqINIA9e0R+J22zQ8+EPBJWoCkSuCcm5FR55BbMKqRk2CrvC5LxgYlMnhiDUypvtIkevHc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IwwRakfh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IwwRakfh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4FD2C4CECD; Wed, 25 Sep 2024 12:15:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727266509; bh=RjfI/WLDaDkKY3bNpnRvp6mIPeVCIol/nkLfahx/6R8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IwwRakfhNdxyZRnozsRlBXsfEu45GK7pKqJUdsFGlDbcBo6qSEXlR+R6HiE/L07aD QUQ9B0KRWMuUxkWpVLmxivHPsbi5f+1Ed5juL5EMgQ3tmfyp13LXHCB3LlYS9gBIlm /15pq2B5STRQ2i6anjONjHp4eG0v7tjsg7rD3SEw5cIL/kbslS790r1T5s/CogeKL3 TcD4xdfFnkF/4OVzER8yNlHzk4b+pGfmiYEiUu+w6p5EpDrImJVeEtM7+XFjBkCNGL SKKoGfM9fxOg7lBB8wBqjWNi78honceyV8XTBBHsbn2b05QSKKkBbpese06Krw6YOd hHQOY1j7ktVdw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Marc Gonzalez , Caleb Connolly , Bjorn Andersson , Will Deacon , Sasha Levin , robdclark@gmail.com, joro@8bytes.org, iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.6 078/139] iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux Date: Wed, 25 Sep 2024 08:08:18 -0400 Message-ID: <20240925121137.1307574-78-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240925121137.1307574-1-sashal@kernel.org> References: <20240925121137.1307574-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.52 Content-Transfer-Encoding: 8bit From: Marc Gonzalez [ Upstream commit 3a8990b8a778219327c5f8ecf10b5d81377b925a ] On qcom msm8998, writing to the last context bank of lpass_q6_smmu (base address 0x05100000) produces a system freeze & reboot. The hardware/hypervisor reports 13 context banks for the LPASS SMMU on msm8998, but only the first 12 are accessible... Override the number of context banks [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation [ 2.563627] arm-smmu 5100000.iommu: address translation ops [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings Specifically, the crashes occur here: qsmmu->bypass_cbndx = smmu->num_context_banks - 1; arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); and here: arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); It is likely that FW reserves the last context bank for its own use, thus a simple work-around is: DON'T USE IT in Linux. If we decrease the number of context banks, last one will be "hidden". Signed-off-by: Marc Gonzalez Reviewed-by: Caleb Connolly Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240820-smmu-v3-1-2f71483b00ec@freebox.fr Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 6e6cb19c81f59..b899a7b7fa935 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -278,6 +278,13 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) u32 smr; int i; + /* + * MSM8998 LPASS SMMU reports 13 context banks, but accessing + * the last context bank crashes the system. + */ + if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13) + smmu->num_context_banks = 12; + /* * Some platforms support more than the Arm SMMU architected maximum of * 128 stream matching groups. For unknown reasons, the additional -- 2.43.0