Re: [RFC PATCH 25/28] x86: Use PIE codegen for the core kernel

Ard Biesheuvel
2024-09-25T21:23:53Z

On Wed, 25 Sept 2024 at 23:09, Andi Kleen <ak@linux.intel.com> wrote:
>
> Ard Biesheuvel <ardb+git@google.com> writes:
> > This substantially reduces the number of relocations that need to be
> > processed when booting a relocatable KASLR kernel.
> >
> > Before (size in bytes of the reloc table):
> >
> > 797372 arch/x86/boot/compressed/vmlinux.relocs
> >
> > After:
> >
> > 400252 arch/x86/boot/compressed/vmlinux.relocs
>
> I don't know why anybody would care about the size of the relocation table?
>

Fair point.

> What matters is what it does to general performance.
>
> Traditionally even on x86-64 PIC/E has a cost and the kernel model
> was intended to avoid that.
>

Is the x86_64 kernel C model specified anywhere, to your knowledge?

> From my perspective this patch kit doesn't fix a real problem,
> it's all risk of performance regression with no gain.
>

It's all in the cover letter and the commit logs so I won't rehash it
here, but I understand that your priorities may be different from
mine.

I'll provide some numbers about the impact on code size. Are there any
other performance related aspects that you think might be impacted by
the use of position independent code generation?